Ulf Schlichtmann

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Chair of Electronic Design Automation-TUM Department of Electrical and Computer Engineering at Technical University of Munich since 2003, Liaison lecturer of the Foundation of German Business (SDW)

Featured Co-authors

Li Zhang
112 publications
Meng Li
40 publications
Yiyu Shi
38 publications
Yang Xu
36 publications
Bing Li
30 publications
Ning Chen
17 publications
Bei Yu
16 publications
Georg Sigl
7 publications
Tsung-Yi Ho
5 publications
Jinglan Liu
5 publications
David Z. Pan
4 publications

Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks

Typical semiconductor chips include thousands of mostly small memories. ...
03/05/2020 ∙ by Felix Last, et al. ∙ 0 ∙ share

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TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix)

With recent advances in reverse engineering, attackers can reconstruct a...
03/02/2020 ∙ by Grace Li Zhang, et al. ∙ 0 ∙ share

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Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

At submicron manufacturing technology nodes, pro- cess variations affect...
05/14/2017 ∙ by Li Zhang, et al. ∙ 0 ∙ share

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PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model

In static timing analysis, clock-to-q delays of flip-flops are considere...
05/14/2017 ∙ by Grace Li Zhang, et al. ∙ 0 ∙ share

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EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

At nanometer manufacturing technology nodes, process variations signific...
05/14/2017 ∙ by Grace Li Zhang, et al. ∙ 0 ∙ share

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Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

At submicron manufacturing technology nodes process variations affect ci...
05/14/2017 ∙ by Grace Li Zhang, et al. ∙ 0 ∙ share

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Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements

Post-silicon clock tuning elements are widely used in high-performance d...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing

Length-matching is an important technique to bal- ance delays of bus sig...
05/14/2017 ∙ by Tsun-Ming Tseng, et al. ∙ 0 ∙ share

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Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards

Length-matching is an important technique to balance delays of bus signa...
05/14/2017 ∙ by Tsun-Ming Tseng, et al. ∙ 0 ∙ share

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Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation

In this paper, we propose a post-processing framework which iteratively ...
05/14/2017 ∙ by Tsun-Ming, et al. ∙ 0 ∙ share

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On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations

Level-sensitive latches are widely used in high- performance designs. Fo...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers

Post-Silicon Tunable (PST) clock buffers are widely used in high perform...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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Timing Model Extraction for Sequential Circuits Considering Process Variations

As semiconductor devices continue to scale down, process vari- ations be...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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On Hierarchical Statistical Static Timing Analysis

Statistical static timing analysis deals with the increasing variations ...
05/14/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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Static Timing Model Extraction for Combinational Circuits

For large circuits, static timing analysis (STA) needs to be performed i...
05/07/2017 ∙ by Bing Li, et al. ∙ 0 ∙ share

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