Maksim Jenihhin | DeepAI

DeepAI AI Chat

Featured Co-authors

Zoya Dyka
21 publications
Peter Langendoerfer
20 publications
Jaan Raik
17 publications
Masoud Daneshtalab
11 publications
Mahdi Taheri
9 publications
Dan Alexandrescu
8 publications
Matteo Sonza Reorda
7 publications
Ali Mahani
7 publications
Said Hamdioui
6 publications
Aneesh Balakrishnan
6 publications
Thomas Lange
6 publications

∙ 05/31/2023

A Novel Fault-Tolerant Logic Style with Self-Checking Capability

We introduce a novel logic style with self-checking capability to enhanc...

0 Mahdi Taheri, et al. ∙

∙ 05/31/2023

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors

Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in s...

0 Mahdi Taheri, et al. ∙

∙ 05/09/2023

A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks

Artificial Intelligence (AI) and, in particular, Machine Learning (ML) h...

0 Mohammad Hasan Ahmadilivani, et al. ∙

∙ 03/14/2023

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

While the role of Deep Neural Networks (DNNs) in a wide range of safety-...

0 Mahdi Taheri, et al. ∙

∙ 03/13/2023

DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment

Deep Neural Networks (DNNs) and their accelerators are being deployed ev...

0 Mohammad Hasan Ahmadilivani, et al. ∙

∙ 03/03/2023

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs

Cyber-Physical Systems (CPSs), such as Unmanned Aerial Vehicles (UAVs), ...

0 Foisal Ahmed, et al. ∙

∙ 03/03/2023

Unsupervised Recycled FPGA Detection Using Symmetry Analysis

Recently, recycled field-programmable gate arrays (FPGAs) pose a signifi...

0 Tanvir Ahmad Tarique, et al. ∙

∙ 12/19/2022

On BTI Aging Rejuvenation in Memory Address Decoders

Memory designs require timing margins to compensate for aging and fabric...

0 Cemil Cem Gursoy, et al. ∙

∙ 04/05/2021

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

Rapidly shrinking technology node and voltage scaling increase the susce...

0 Aneesh Balakrishnan, et al. ∙

∙ 04/05/2021

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

As an alternative to traditional fault injection-based methodologies and...

0 Aneesh Balakrishnan, et al. ∙

∙ 04/05/2021

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

The paper is proposing a methodology for modeling a gate-level netlist u...

0 Aneesh Balakrishnan, et al. ∙

∙ 03/02/2021

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL

The advanced complex electronic systems increasingly demand safer and mo...

0 Ahmet Cagri Bagbaba, et al. ∙

∙ 08/19/2020

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Physical Unclonable Functions (PUFs) are gaining attention in the crypto...

0 Xinhui Lai, et al. ∙

∙ 02/25/2020

PASCAL: Timing SCA Resistant Design and Verification Flow

A large number of crypto accelerators are being deployed with the widesp...

0 Xinhui Lai, et al. ∙

∙ 01/24/2020

Efficient Fault Injection based on Dynamic HDL Slicing Technique

This work proposes a fault injection methodology where Hardware Descript...

0 Ahmet Cagri Bagbaba, et al. ∙

∙ 01/24/2020

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Along with the complexity of electronic systems for safety-critical appl...

0 Ahmet Cagri Bagbaba, et al. ∙

∙ 11/29/2019

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

The recent trends for nanoelectronic computing systems include machine-t...

0 Maksim Jenihhin, et al. ∙

∙ 09/01/2019

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

The gigantic complexity and heterogeneity of today's advanced cyber-phys...

0 Maksim Jenihhin, et al. ∙

∙ 08/08/2019

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors

Recent safety standards set stringent requirements for the target fault ...

0 Adeboye Stephen Oyeniran, et al. ∙

∙ 08/01/2019

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Trends in advanced electronic systems' design have a notable impact on d...

0 Maksim Jenihhin, et al. ∙

∙ 07/29/2019

Mixed-level identification of fault redundancy in microprocessors

A new high-level implementation independent functional fault model for c...

0 Adeboye Stephen Oyeniran, et al. ∙