Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

04/05/2021
by   Aneesh Balakrishnan, et al.
0

Rapidly shrinking technology node and voltage scaling increase the susceptibility of Soft Errors in digital circuits. Soft Errors are radiation-induced effects while the radiation particles such as Alpha, Neutrons or Heavy Ions, interact with sensitive regions of microelectronic devices/circuits. The particle hit could be a glancing blow or a penetrating strike. A well apprehended and characterized way of analyzing soft error effects is the fault-injection campaign, but that typically acknowledged as time and resource-consuming simulation strategy. As an alternative to traditional fault injection-based methodologies and to explore the applicability of modern graph based neural network algorithms in the field of reliability modeling, this paper proposes a systematic framework that explores gate-level abstractions to extract and exploit relevant feature representations at low-dimensional vector space. The framework allows the extensive prediction analysis of SEU type soft error effects in a given circuit. A scalable and inductive type representation learning algorithm on graphs called GraphSAGE has been utilized for efficiently extracting structural features of the gate-level netlist, providing a valuable database to exercise a downstream machine learning or deep learning algorithm aiming at predicting fault propagation metrics. Functional Failure Rate (FFR): the predicted fault propagating metric of SEU type fault within the gate-level circuit abstraction of the 10-Gigabit Ethernet MAC (IEEE 802.3) standard circuit.

READ FULL TEXT
research
04/05/2021

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

As an alternative to traditional fault injection-based methodologies and...
research
04/05/2021

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

The paper is proposing a methodology for modeling a gate-level netlist u...
research
12/25/2016

Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits

High energy particles from cosmic rays or packaging materials can genera...
research
02/13/2020

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

With technology scaling, lower supply voltages, and higher operating fre...
research
07/29/2021

ReCo1: A Fault resilient technique of Correlation Sensitive Stochastic Designs

In stochastic circuits, major sources of error are correlation errors, s...
research
10/12/2022

Statistical Modeling of Soft Error Influence on Neural Networks

Soft errors in large VLSI circuits pose dramatic influence on computing-...
research
06/17/2009

Maximum Error Modeling for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis

The application of current generation computing machines in safety-centr...

Please sign up or login with your details

Forgot password? Click here to reset