b'Hasan Hassan'

research

∙ 03/13/2023

Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation

DRAM is the primary technology used for main memory in modern systems. U...

0 Hasan Hassan, et al. ∙

research

∙ 11/10/2022

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips

To understand and improve DRAM performance, reliability, security and en...

0 Ataberk Olgun, et al. ∙

research

∙ 09/21/2022

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

DRAM is the building block of modern main memory systems. DRAM cells mus...

0 Abdullah Giray Yağlıkçı, et al. ∙

research

∙ 07/27/2022

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture

There are two major sources of inefficiency in computing systems that us...

0 Ataberk Olgun, et al. ∙

research

∙ 07/27/2022

A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations

The memory controller is in charge of managing DRAM maintenance operatio...

0 Hasan Hassan, et al. ∙

research

∙ 06/20/2022

Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices

RowHammer is a circuit-level DRAM vulnerability, where repeatedly activa...

0 A. Giray Yaglıkçı, et al. ∙

research

∙ 06/01/2022

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques

DRAM-based main memory is used in nearly all computing systems as a majo...

0 Ataberk Olgun, et al. ∙

research

∙ 01/04/2022

DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

Random number generation is an important task in a wide variety of criti...

0 F. Nisa Bostancı, et al. ∙

research

∙ 10/29/2021

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

Processing-using-memory (PuM) techniques leverage the analog operation o...

0 Ataberk Olgun, et al. ∙

research

∙ 10/20/2021

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications

The RowHammer vulnerability in DRAM is a critical threat to system secur...

0 Hasan Hassan, et al. ∙

research

∙ 10/19/2021

A Deeper Look into RowHammer`s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

RowHammer is a circuit-level DRAM vulnerability where repeatedly accessi...

0 Lois Orosa, et al. ∙

research

∙ 06/10/2021

CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations

DRAM is the dominant main memory technology used in modern computing sys...

0 Lois Orosa, et al. ∙

research

∙ 05/17/2021

MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations

This paper introduces the first open-source FPGA-based infrastructure, M...

0 Nandita Vijaykumar, et al. ∙

research

∙ 02/11/2021

BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

Aggressive memory density scaling causes modern DRAM devices to suffer f...

0 Abdullah Giray Yağlıkçı, et al. ∙

research

∙ 09/17/2020

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Increasing single-cell DRAM error rates have pushed DRAM manufacturers t...

0 Minesh Patel, et al. ∙

research

∙ 05/27/2020

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

In order to shed more light on how RowHammer affects modern and future d...

0 Jeremie S. Kim, et al. ∙

research

∙ 05/26/2020

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

DRAM is the prevalent main memory technology, but its long access latenc...

0 Haocong Luo, et al. ∙

research

∙ 04/03/2020

TRRespass: Exploiting the Many Sides of Target Row Refresh

After a plethora of high-profile RowHammer attacks, CPU and DRAM vendors...

0 Pietro Frigo, et al. ∙

research

∙ 10/15/2019

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators

Recently, many studies proposed CNN accelerator architectures with custo...

0 Syed M. A. H. Jafri, et al. ∙

research

∙ 02/19/2019

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices

Low-cost devices are now commonplace and can be found in diverse environ...

0 Lois Orosa, et al. ∙

research

∙ 10/22/2018

Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions

Synchronous Mirroring (SM) is a standard approach to building highly-ava...

0 Arash Tavakkol, et al. ∙

research

∙ 09/18/2018

Shouji: A Fast and Efficient Pre-Alignment Filter for Sequence Alignment

Motivation: The ability to generate massive amounts of sequencing data c...

0 Mohammed Alser, et al. ∙

research

∙ 09/18/2018

Shouji: Fast and Efficient Computation of Banded Sequence Alignment

Motivation: The ability to generate massive amounts of sequencing data c...

0 Mohammed Alser, et al. ∙

research

∙ 09/18/2018

SLIDER: Fast and Efficient Computation of Banded Sequence Alignment

Motivation: The ability to generate massive amounts of sequencing data c...

0 Mohammed Alser, et al. ∙

research

∙ 08/13/2018

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

We propose a new DRAM-based true random number generator (TRNG) that lev...

0 Jeremie S. Kim, et al. ∙

research

∙ 08/13/2018

D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices

DRAM provides a promising substrate for generating random numbers due to...

0 Jeremie S. Kim, et al. ∙

research

∙ 07/13/2018

What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study

Main memory (DRAM) consumes as much as half of the total system power in...

0 Saugata Ghose, et al. ∙

research

∙ 05/08/2018

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency

This paper summarizes the idea of ChargeCache, which was published in HP...

0 Hasan Hassan, et al. ∙

research

∙ 05/08/2018

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

This paper summarizes the SoftMC DRAM characterization infrastructure, w...

0 Hasan Hassan, et al. ∙

research

∙ 05/08/2018

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

This paper summarizes our work on experimental characterization and anal...

0 Kevin K. Chang, et al. ∙

research

∙ 05/08/2018

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips

This article summarizes key results of our work on experimental characte...

0 Kevin K. Chang, et al. ∙

research

∙ 06/10/2017

LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures

Processing-in-memory (PIM) architectures have seen an increase in popula...

0 Amirali Boroumand, et al. ∙

research

∙ 05/29/2017

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

The energy consumption of DRAM is a critical concern in modern computing...

0 Kevin K. Chang, et al. ∙

research

∙ 11/30/2016

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM

Bitwise operations are an important component of modern day programming....

0 Vivek Seshadri, et al. ∙

research

∙ 09/23/2016

Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns

DRAM-based memory is a critical factor that creates a bottleneck on the ...

0 Hasan Hassan, et al. ∙

research

∙ 04/06/2016

GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping

Motivation: High throughput DNA sequencing (HTS) technologies generate a...

0 Mohammed Alser, et al. ∙

Hasan Hassan

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