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10/29/2022
MinUn: Accurate ML Inference on Microcontrollers
Running machine learning inference on tiny devices, known as TinyML, is ...
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06/26/2022
Annotated Speech Corpus for Low Resource Indian Languages: Awadhi, Bhojpuri, Braj and Magahi
In this paper we discuss an in-progress work on the development of a spe...
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05/06/2022
Aksharantar: Towards building open transliteration tools for the next billion users
We introduce Aksharantar, the largest publicly available transliteration...
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07/08/2021
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Recent breakthroughs in ML have produced new classes of models that allo...
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04/01/2021
Multilingual and code-switching ASR challenges for low resource Indian languages
Recently, there is increasing interest in multilingual automatic speech ...
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05/19/2020
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
Computers continue to diversify with respect to system designs, emerging...
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05/23/2019
In-DRAM Bulk Bitwise Execution Engine
Many applications heavily use bitwise operations on large bitvectors as ...
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02/19/2019
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices
Low-cost devices are now commonplace and can be found in diverse environ...
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06/08/2018
PipeDream: Fast and Efficient Pipeline Parallel DNN Training
PipeDream is a Deep Neural Network(DNN) training system for GPUs that pa...
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05/15/2018
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
This paper summarizes the ideas and key concepts in MISE (Memory Interfe...
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05/08/2018
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
This paper summarizes the idea of ChargeCache, which was published in HP...
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05/07/2018
RowClone: Accelerating Data Movement and Initialization Using DRAM
In existing systems, to perform any bulk data movement operation (copy o...
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05/04/2018
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
This paper summarizes the idea of Subarray-Level Parallelism (SALP) in D...
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05/04/2018
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which w...
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05/04/2018
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which...
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11/30/2016
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
Bitwise operations are an important component of modern day programming....
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10/30/2016
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Variation has been shown to exist across the cells within a modern DRAM ...
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10/30/2016
The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
In existing systems, the off-chip memory interface allows the memory con...
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05/20/2016
Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems
In most modern systems, the memory subsystem is managed and accessed at ...
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03/28/2016