
FunSAT: Functional CorruptibilityGuided SATBased Attack on Sequential Logic Encryption
The SAT attack has shown to be efficient against most combinational logi...
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GFFlush: A GF(2) Algebraic Attack on Secure Scan Chains
Scan chains provide increased controllability and observability for test...
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A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
This paper presents a dynamic network rewiring (DNR) method to generate ...
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Formal Verification of Flow Equivalence in Desynchronized Designs
Seminal work by Cortadella, Kondratyev, Lavagno, and Sotiriou includes a...
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DeepnCheap: An Automated Search Framework for Low Complexity Deep Learning
We present DeepnCheap – an opensource AutoML framework to search for ...
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qBSA: Logic Design of a 32bit BlockSkewed RSFQ Arithmetic Logic Unit
Single flux quantum (SFQ) circuits are an attractive beyondCMOS technol...
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Predefined Sparsity for LowComplexity Convolutional Neural Networks
The high energy cost of processing deep convolutional neural networks im...
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SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol
The risk of soft errors due to radiation continues to be a significant c...
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Neural Network Training with Approximate Logarithmic Computations
The high computational complexity associated with training deep neural n...
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A Predefined Sparse Kernel Based Convolution for Deep CNNs
The high demand for computational and storage resources severely impede ...
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A Predefined Sparse Kernel Based Convolutionfor Deep CNNs
The high demand for computational and storage resources severely impede ...
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Automatic Conversion from Flipflop to 3phase Latchbased Designs
Latchbased designs have many benefits over their flipflop based counte...
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PreDefined Sparse Neural Networks with Hardware Acceleration
Neural networks have proven to be extremely powerful tools for modern ar...
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Morse Code Datasets for Machine Learning
We present an algorithm to generate synthetic datasets of tunable diffic...
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A Highly Parallel FPGA Implementation of Sparse Neural Network Training
We demonstrate an FPGA implementation of a parallel and reconfigurable a...
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Characterizing Sparse Connectivity Patterns in Neural Networks
We propose a novel way of reducing the number of parameters in the stora...
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Accelerating Training of Deep Neural Networks via Sparse Edge Processing
We propose a reconfigurable hardware architecture for deep neural networ...
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Peter A. Beerel
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