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A2P-MANN: Adaptive Attention Inference Hops Pruned Memory-Augmented Neural Networks
In this work, to limit the number of required attention inference hops i...
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BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification
In this paper, first, a hardware-friendly pruning algorithm for reducing...
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A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
This paper presents a dynamic network rewiring (DNR) method to generate ...
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SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning
Machine learning models differ in terms of accuracy, computational/memor...
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Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis
This paper aims at integrating three powerful techniques namely Deep Lea...
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NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework
The shrinking of transistor geometries as well as the increasing complex...
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CSM-NN: Current Source Model Based Logic Circuit Simulation – A Neural Network Approach
The miniaturization of transistors down to 5nm and beyond, plus the incr...
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Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space
Recent advances in the field of artificial intelligence have been made p...
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qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit
Single flux quantum (SFQ) circuits are an attractive beyond-CMOS technol...
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Pre-defined Sparsity for Low-Complexity Convolutional Neural Networks
The high energy cost of processing deep convolutional neural networks im...
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Run-time Deep Model Multiplexing
We propose a framework to design a light-weight neural multiplexer that ...
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Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning
Energy consumption is one of the most critical concerns in designing com...
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Coarse2Fine: A Two-stage Training Method for Fine-grained Visual Classification
Small inter-class and large intra-class variations are the main challeng...
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Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework
Machine learning applied to architecture design presents a promising opp...
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Energy-Aware Scheduling of Task Graphs with Imprecise Computations and End-to-End Deadlines
Imprecise computations provide an avenue for scheduling algorithms devel...
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BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services
Recent studies have shown the latency and energy consumption of deep neu...
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Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays
Memory accounts for a considerable portion of the total power budget and...
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Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
Approximate Logic Synthesis (ALS) is the process of synthesizing and map...
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Towards Collaborative Intelligence Friendly Architectures for Deep Learning
Modern mobile devices are equipped with high-performance hardware resour...
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Space Expansion of Feature Selection for Designing more Accurate Error Predictors
Approximate computing is being considered as a promising design paradigm...
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Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline
Energy efficiency is one of the most critical design criteria for modern...
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Gradient Agreement as an Optimization Objective for Meta-Learning
This paper presents a novel optimization method for maximizing generaliz...
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A Meta-Learning Approach for Custom Model Training
Transfer-learning and meta-learning are two effective methods to apply k...
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NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference
Deep neural networks have been successfully deployed in a wide variety o...
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Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications
Major advancements in building general-purpose and customized hardware h...
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VIBNN: Hardware Acceleration of Bayesian Neural Networks
Bayesian Neural Networks (BNNs) have been proposed to address the proble...
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JointDNN: An Efficient Training and Inference Engine for Intelligent Mobile Cloud Computing Services
Deep neural networks are among the most influential architectures of dee...
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A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA
With ever-increasing application of machine learning models in various d...
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FFT-Based Deep Learning Deployment in Embedded Systems
Deep learning has delivered its powerfulness in many application domains...
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High-Performance FPGA Implementation of Equivariant Adaptive Separation via Independence Algorithm for Independent Component Analysis
Independent Component Analysis (ICA) is a dimensionality reduction techn...
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