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09/01/2023
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU
The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for ...
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04/30/2023
Experiences of running an HPC RISC-V testbed
Funded by the UK ExCALIBUR H&ES exascale programme, in early 2022 a RISC...
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04/20/2023
Backporting RISC-V Vector assembly
Leveraging vectorisation, the ability for a CPU to apply operations to m...
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04/20/2023
Test-driving RISC-V Vector hardware for HPC
Whilst the RISC-V Vector extension (RVV) has been ratified, at the time ...
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09/02/2022
Performance of the Vipera framework for DSLs on micro-core architectures
Vipera provides a compiler and runtime framework for implementing dynami...
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02/03/2021
Compact Native Code Generation for Dynamic Languages on Micro-core Architectures
Micro-core architectures combine many simple, low memory, low power-cons...
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11/10/2020
Benchmarking micro-core architectures for detecting disasters at the edge
Leveraging real-time data to detect disasters such as wildfires, extreme...
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10/04/2020