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VTA: An Open Hardware-Software Stack for Deep Learning

07/11/2018
by   Thierry Moreau, et al.
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Hardware acceleration is an enabler for ubiquitous and efficient deep learning. With hardware accelerators being introduced in datacenter and edge devices, it is time to acknowledge that hardware specialization is central to the deep learning system stack. This technical report presents the Versatile Tensor Accelerator (VTA), an open, generic, and customizable deep learning accelerator design. VTA is a programmable accelerator that exposes a RISC-like programming abstraction to describe operations at the tensor level. We designed VTA to expose the most salient and common characteristics of mainstream deep learning accelerators, such as tensor operations, DMA load/stores, and explicit compute/memory arbitration. VTA is more than a standalone accelerator design: it's an end-to-end solution that includes drivers, a JIT runtime, and an optimizing compiler stack based on TVM. The current release of VTA includes a behavioral hardware simulator, as well as the infrastructure to deploy VTA on low-cost FPGA development boards for fast prototyping. By extending the TVM stack with a customizable, and open source deep learning hardware accelerator design, we are exposing a transparent end-to-end deep learning stack from the high-level deep learning framework, down to the actual hardware design and implementation. This forms a truly end-to-end, from software-to-hardware open source stack for deep learning systems.

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1 Introduction

Hardware specialization is a powerful way to accelerate a known set of applications and workloads. Unfortunately, deep learning is anything but a static field, and machine learning community rapidly changes the software they use to write models, the architecture of models themselves, the operators used by said models, and the data types they operate over.

The research community has primarily focused on two approaches for accelerator designs, fixed function accelerators and programmable accelerators (also known as Domain-Specialized Accelerators). Current solutions offer compelling peak performance, but often fail to integrate into the evolving machine learning landscape.

Fixed-model accelerators are commonly spatially and statically laid out, offering attractive performance for certain workloads. Unfortunately, the static nature of this approach rules out the reuse of hardware resources, limiting support for larger or newer models.

In contrast, programmable accelerators [6] offer far more flexibility by leveraging ISAs. Due to the programmable nature of these accelerators, achieving peak performance requires a competent deep learning compiler that can map a large number of workloads onto a fixed set of hardware intrinsics. Consequently, customizing behavior of these accelerators, even when open-sourced, is highly dependent on the availability of a transparent and modular software stack.

A central challenge in prior work is linking innovations in specialization to the rapidly changing software of machine learning. This challenge is not specific to computer architecture; it is present at all levels of the stack. An end-to-end approach requires integration between frameworks, systems, compilers, and architecture in order to execute state of the art machine learning using hardware acceleration. Peak FLOPs only provide value if a programmer can access them.

We present VTA (Versatile Tensor Accelerator): an explicitly programmed architecture paired with a capable JIT compiler and runtime that can evolve in tandem with deep learning models without sacrificing the advantages of specialization. VTA makes the following contributions:

  • A programmable accelerator design that exposes a two-level programming interface: a high-level task ISA to allow explicit task scheduling by the compiler stack, and a low-level microcode ISA to provide software-defined operational flexibility. In addition the VTA architecture is fully parameterizable: the hardware intrinsics, memories, and data types can be customized to adapt to the hardware backend requirements.

  • An extensible runtime system for heterogeneous execution that performs JIT compilation of microcoded kernels to provide operational flexibility. The VTA runtime has allowed us, for instance, to extend the functionality of VTA’s original computer vision-centric design to support operators found in style transfer applications without requiring any modifications to the hardware.

  • A schedule auto-tuning platform that can optimize data access and data reuse in order to rapidly adapt to changes in the underlying hardware and changes in workload diversity.

Fig. 1: VTA provides flexibility with respect to hardware targets and deep learning models. This flow diagram shows the steps in adapting a given model to a hardware backend by exploring VTA hardware configurations, and performing operator autotuning on the top hardware candidates. This process generates the pieces necessary to deploy VTA in any deep learning framework.

We demonstrate VTA’s flexibility by adapting different workloads for two edge FPGAs. Figure 1 presents how to map a workload to FPGAs using the VTA architecture and runtime. This process explores VTA hardware variants, and performs software autotuning for each candidate design. The resulting design and customized software binaries can be easily integrated into a deep learning framework. Finally, we evaluate the full system, demonstrating VTA’s ability to outperform edge GPUs with edge FPGAs on inference workloads.

2 VTA Hardware-Software Stack Overview

Running an end-to-end workload on VTA requires a complete software stack that can map high-level models down to the programming interface exposed by VTA. We outline the layers of the VTA system stack below, which we built into the Apache TVM deep learning compiler stack.

Fig. 2: Overview of the software stack built for VTA. We leverage the Apache TVM compiler stack to target VTA.
Framework.

Frameworks allow programmers to easily express models in a declarative fashion and perform training at scale on standard datasets. Frameworks like TensorFlow, PyTorch, MxNet have gained widespread adoption, allowing the community to easily share, and deploy models. TVM’s ability to ingest models from these popular frameworks, enables generic compilation from frameworks to VTA.

Relay Graph Optimizer.

Relay [7] is TVM’s high level program representation. Relay generalizes the computation graphs used by prior frameworks and deep learning compilers into a full programming language. The Relay optimization pipeline performs generic optimizations such as operator fusion and partial evaluation. Relay’s design is focused on extensibility, a property we use to extend Relay with a set of optimizations specific to VTA. When targeting VTA we quantize inputs to match VTA’s low precision data types, transform data layout, maximize data reuse, and transform input and weight data layouts to utilize VTA’s tensor intrinsics.

TVM Operator Optimizer.

TVM [3] automates the tedious process of scheduling workloads onto VTA accelerator variants. Scheduling is important for multiple reasons. First, it tiles the computation to maximize data reuse. Second, it inserts thread parallelism that VTA’s runtime can translate into task-level pipeline parallelism. Third, it partitions operators into sub-computations which can be mapped to high-level hardware intrinsics such as bulk DMA load or GEMM. TVM incorporates AutoTVM [4], an automated schedule optimizer. We rely upon AutoTVM to guide our hardware candidate exploration search for the best VTA candidates given a workload.

JIT Compiler and Runtime.

The runtime performs JIT compilation of the accelerator binaries and manages heterogeneous execution between the CPU and VTA. The JIT compiler abstracts binary compatibility by introducing one level of indirection. We describe the runtime in more details in Section 3.2.

Hardware architecture.

VTA is a parameterizable accelerator that accelerates the bulk of the deep learning compute graph. VTA is explicitly programmed by the compiler stack using a two-level programming interface. The architecture is parameterized by the size of the GEMM core, the SRAM shapes, and data type widths. A parameterized hardware architecture makes it possible to retarget the same design to devices with different hardware resources. We describe VTA in more details in Section 3.1.

Fig. 3: The VTA hardware organization. VTA is composed of modules that communicate via queues and SRAMs. This defines a task pipeline, which helps maximize compute resource utilization.
Fig. 4: The VTA high-level instruction fields. LOAD and STORE

instructions perform 2D strided DMA reads/writes between DRAM and SRAM.

GEMM instructions are used to matrix multiplication, 2D convolutions, etc. while ALU instructions can perform a wide range of activation, normalization, and pooling tasks.

3 VTA Architecture and JIT Runtime

A successful implementation of a flexible deep learning accelerator requires co-design of the hardware with the software stack. We describe at a high level two components that were co-designed to achieve this goal: the VTA hardware architecture, and the VTA JIT compiler and runtime.

3.1 Hardware Architecture

Figure 3 gives a high-level overview of the VTA hardware organization. VTA is composed of four modules: fetch, load, compute, and store. Together, these modules define a task pipeline, which enables high compute resource utilization on compute-bound workloads, and high memory bandwidth utilization on memory-bound workloads. These modules communicate over command queues and on-chip shared memories (SRAMs) that act as uni-directional data channels. Accesses to these memories are synchronized via dependency queues to prevent data hazards such as Read After Write (RAW) and Write After Read (WAR). Finally, the 3-stage architecture (load-compute-store) can be used to build task pipelines of arbitrary depth as long as dependencies are properly managed.

Parameterizability. The VTA architecture is fully parameterizable: the shape of the GEMM tensor intrinsic can be modified to influence the utilization of hardware resources. Modifying the shape of the input, weight, and accumulator tensors that feed the GEMM unit directly affects how many multipliers to instantiate and how wide SRAMs ports need to be. In addition, each data type can customized to a different integer precision: weight and input types can be 8-bits or fewer, while the accumulation type can be 32-bits or fewer. Control of integer precision lets us scale arithmetic density on chip when resources are constrained.

Exposing Task-Level Pipeline Parallelism. Task-Level Pipeline Parallelism (TLPP) is an important feature in the VTA architecture, because it enables simultaneous use of compute and memory resources to maximize their utilization. TLPP is based on the paradigm of access-execute decoupling [8]. To extract TLPP, we partition tasks into two mutually-exclusive execution contexts, so that concurrent load, compute, and store operations do not interfere with one another. This partitioning is easily achieved in TVM using virtual threads [3]. To guarantee timely and correct execution for decoupled access-execute instruction streams, we encode dependency information into instructions. This effectively results in memory latency hiding on compute-bound workloads (e.g. 2d convolutions).

Task-Level ISA. VTA supports a high-level task ISA that encodes multi-cycle compute and memory operations, including LOAD, GEMM, ALU, and STORE instructions described in Figure 4. LOAD and STORE instructions describe how data from DRAM is loaded and stored into on-chip SRAMs. Strided memory access is supported to load tensor tiles without modifying memory layout. GEMM and ALU instructions invoke micro-coded kernels, based on micro-op instructions, which describe the data-access patterns that define a given deep learning operator.

We illustrate a simple execution pipeline in VTA below:

  • The fetch module loads task instructions from DRAM and dispatches them, according to the instruction type, to the corresponding command queues connected to load, compute, and store modules.

  • The load module loads input, weight, and bias tensor tiles from DRAM into on-chip memories.

  • The compute module loads a micro-coded kernel from DRAM into on-chip memory. Micro-coded kernels are based on micro-ops that describe data access patterns for inputs, weights, and biases.

  • The compute module executes the micro-coded kernel to perform either a dense linear algebra computation via the GEMM core or a pairwise arithmetic operations via the Tensor ALU.

  • The store module reads results processed by the compute module and writes them to DRAM.

Fig. 5: The GEMM core can perform one dense matrix multiplication over an input tensor and a weight tensor, and add the result into a register file tensor. The data addressing pattern is specified by a micro-coded sequence: this allows us to map different deep learning operators onto a single fixed-sized matrix-matrix multiplication intrinsic.

Compute Module. Two functional units perform operations on the register file: the tensor ALU and the GEMM core. The tensor ALU performs element-wise tensor operations such as addition, activation, normalization, and pooling tasks. The GEMM core performs high-arithmetic intensity matrix multiplication over input and weight tensors to implement common deep learning operators such as 2D convolutions, or fully connected layers.

The GEMM core performs matrix multiply operations at a pipelined rate of one input-weight matrix multiplication per cycle. Its logic is implemented as parallel vector dot-product using reduction trees, but can be substituted with other implementations such as systolic arrays. The GEMM core defines a low-level tensor

hardware intrinsic which is exposed to the TVM compiler stack. TVM uses tensorization [3]: an automated approach to mapping deep learning operators such as 2d convolution down to fixed tensor hardware intrinsics.

Microcode ISA. The compute core reads instructions from the micro-op cache, which describe how computation is performed over data. Figure 5 details how the GEMM core performs computation over data stored in the input, weight, and accumulator memories. These micro-ops provide no control flow. Therefore, instructions need to be unrolled to express repeatable data access stencils. There are two types of compute micro-ops: ALU and GEMM operations. To minimize the footprint of micro-op kernels while avoiding the need for control-flow instructions, the compute core executes micro-op sequences inside a two-level nested loop that computes the location of each tensor register via an affine function. This compression approach helps reduce the micro-ops footprint when sent to the accelerator.

3.2 JIT Runtime System

VTA’s JIT runtime enables cooperative execution of deep learning workloads between a CPU host and the accelerator. The JIT runtime design follows five objectives: (1) enable heterogeneous execution, (2) lower compiler design complexity, (3) overcome physical limitations, (4) reduce binary bloat, (5) future proofing.

Heterogeneous execution. One challenge present in fixed function accelerators is model evolution, because most of these accelerators are built for fixed models. Heterogeneous execution overcomes this limitation by properly scheduling operators into targets (e.g., CPUs or VTA), depending on their affinity for different types of operators. For instance, it is well known that the first convolutional layer in most CNNs contains operators with low arithmetic intensity that perform well on CPUs. Another motivation behind heterogeneous execution is providing a fallback mechanism for supporting emerging operators that are not yet supported by VTA.

Compiler Design. By adding a level of indirection, code JIT-ting eliminates the need to write compiler code-generation backends which can be tedious to maintain for different programmable accelerators. The JIT compiler exposes a high-level API to TVM to lower schedules onto, abstracting away VTA variant-specific architectural details. This lets us extend the TVM compiler support we built for VTA to cover future variants of different shapes and sizes.

Physical Limitations. The JIT runtime generates and manages micro-kernels on the fly. It controls when to load kernels from DRAM into the accelerator limited micro-op cache. This eliminates micro-op memory physical limitations and lets us support large models, even if all micro-kernels for all layers do not fit in SRAM all at once. It also lets us trade area used by the micro-op cache for other resources such as data storage, or compute units.

Binary bloat. Delaying micro-kernel generation to the JIT compilation stage minimizes binary bloat. Since VTA’s architecture has limited support for control flow, micro-kernels have to be unrolled which can produce fairly large binaries. In addition, micro-kernel code JIT-ting expresses binaries for heterogeneous execution in a single-ISA: instead of shipping a hybrid binary, we just ship one CPU binary that performs accelerator binary JIT-ting.

Future proofing.

Advancements in deep learning have outlined the prevalence of dynamic neural network workloads that incorporate control flow. Additionally, advances in systems show trends towards heterogeneous multi-accelerator systems and scale-out acceleration. Having a runtime that handles dynamic decisions across heterogeneous platforms will keep the design of hardware accelerators like VTA simple, and constrain support for future models to being a mostly software-defined problem.

4 VTA Hierarchical Optimization

Fig. 6:

Schedule exploration with XGBoost for a single ResNet-18 layer on Ultra-96. Eight VTA design candidates with (2,16)x(16,16) and (8,8)x(8,8) GEMM intrinsic at W8A8 are considered. Layer is conv2d: IC=256, OC=256, H=W=14, KW=KH=3, stride=(1,1), padding=(0,0).

4.1 Hardware Exploration for Varying FPGA Sizes

One way to showcase VTA’s architecture flexibility is to target different FPGA platforms. FPGAs are becoming more accessible than ever, with sub-$100 development boards, and FPGA cloud computing instances becoming ubiquitous.

The VTA design offers multiple architectural customization parameters that are listed in Figure 1. Architectural knobs include GEMM hardware intrinsic shape, data types, number of parallel arithmetic units in the tensor ALU, ALU operations, BRAM distribution between on-chip memories. Circuit knobs include degree of hardware pipelining to close timing at higher frequencies, and PLL frequency. These customization knobs define a hardware design space with 100s to 1000s of individual designs. This design space can be exhaustively explored to find the best candidate for a particular workload. We perform this exploration in a sequence of stratified steps. First we use a simple FPGA resource model to prune infeasible VTA parameterizations. After pruning, each candidate hardware design is compiled, placed, and routed. We pick the best feasible design for each combination, but typically our exploration returns a handful of promising candidates – the rest of the designs either yield low peak performance or fail placement, routing, or timing closure. For this final set of designs, we generate optimized software, using operator autotuning [4], and use this software to obtain the workload’s performance profile.

An analytical model of peak performance is used to initially filter hardware designs based on theoretical throughput and frequency assuming compute resources are 100% utilized. However, assuming 100% utilization of compute resources by a particular operator is often inaccurate. For example, depending on the workload mix, operators like conv2d with large window sizes may exhibit high arithmetic intensity (measured in Op/Byte). Operations with high arithmetic intensity translate to high utilization, and therefore are close to peak performance. Operators which exhibit low arithmetic intensity, like conv2d, with a window size of 1, are memory bandwidth constrained. In these situations we are able to use task-level pipeline parallelism to mitigate performance loss.

Fig. 7: Example of hardware design exploration and schedule autotuning on a complete ResNet-18 inference workload run on Ultra96 FPGA. The exploration begins with promising VTA hardware variants and converges to the optimal hardware design while using a fraction of the optimization time required to exhaustively evaluate each hardware design.

4.2 Schedule Exploration for Operator Autotuning

Schedule autotuning is the process by which an automated search algorithm attempts to optimize a given program or workload towards peak hardware performance. We perform autotuning by applying different memory tiling, loop transformations (e.g. splitting, reordering, unrolling), vectorization/tensorization, and parallelization strategies [4]. We then use the TVM compiler to express schedule templates for each operator (e.g. conv2d, conv2d_transpose, group_conv2d, fc) we support in hardware. We use TVM’s automated scheduling library to obtain schedules that maximize performance for a given combination of operator, tensor shape, and hardware parameterization.

Figure 6 shows the autotuning search process when optimizing different VTA hardware candidates for a single ResNet layer. We used the XGBoost [1] search algorithm to find the best schedules for each hardware variant in a limited number of trials. Each workload’s layers are then tuned for each hardware candidate. Aggregate inference time is used to select the VTA hardware variant that is best for a given model.

It takes several hours to exhaustively tune a network on a single hardware variant. Given the large number of VTA hardware designs to test, and model architectures to support, autotuning search quickly becomes intractable without careful design. Minimizing full-network autotuning time across multiple hardware candidates introduces a hierarchical prioritization problem

. We approach this challenge by applying a hyperparameter optimization technique, based on

SuccessiveHalving [5]

. Instead of choosing among hyperparameters that define a network architecture, we apply this technique to choose among VTA design candidates. We simultaneously inspect how the relative performance of each hardware design evolves for a given workload, over each iteration of the optimization algorithm. Throughout optimization we use a round-robin policy to update latency estimates across all operators for each hardware design.

4.3 Full Network Optimization Case Study

We show in Figure 7 an example of hierarchical optimization for the ResNet-18 workload, based on the hardware exploration and schedule exploration techniques described before. We perform these optimizations over a set VTA candidates generated using W8A8 (8-bit weights, 8-bit activations) data representations. We select eight promising hardware candidates, and apply SuccessiveHalving to prune designs that do not appear promising. Similar to hyperparameter optimization for neural network training, this is a difficult task, as the relative performance differences between hardware designs may be small early on. After a moderate number of iterations, SuccessiveHalving is able to converge to the best candidate hardware design.

This case study showcases VTA’s ability to quickly navigate a non-trivial space of accelerator configurations for a given workload. As accelerator configurations change, so does the software that programs it. This joint-optimization problem can only be solved with a flexible stack.

5 Evaluation

As the landscape of deep learning continues to evolve, it is important to support emerging models. We evaluate VTA’s ability to support two novel model architectures beyond standard deep convolution nets. First, we evaluate MobileNet, a recent model architecture that uses grouped convolution to reduce the total computation overhead of the network. We evaluate a variant of MobileNet we call MobileNetG that groups channels by the vector factor of the VTA’s GEMM core. Second, we implement a Generative Adversarial Network (DCGAN) model that is used for image-to-image translation and generation.

Both models require non-trivial extensions to support new operators. MobileNetG requires support for grouped convolutions that exhibit block sparse patterns on channel groups. DCGAN requires support for 2D convolution transpose which has a spatial sparsity pattern. Accelerators must support these access patterns to avoid unnecessary computations and achieve maximum performance. The runtime can readily make use of schedules to generate micro-kernels that support these access patterns without changing the hardware.

We integrated VTA into Apache TVM and evaluated a variety of deep learning models on a set of edge FPGA devices with different resource budgets. We imported all models from MxNet [2] a deep learning framework used by Amazon. It is worth noting Relay’s model importers provide access to a wide variety of other front-ends, and VTA is not limited to MxNet.

Fig. 8: End to end performance evaluation over multiple CPU, GPU and FPGA-equipped edge systems. For comparable systems, VTA provides a significant performance edge over conventional CPU and GPU-based inference.

Figure 8 shows a performance comparison across these models, comparing VTA-accelerated execution against a highly optimized ARM CPU and GPU platforms that rely on industry-strength deep learning libraries: ARM ComputeLib (ARM CL) and TVM. The ARM Cortex-A9, ARM Cortex-A53, and Mali-T860 GPU are taken from the Pynq-Z1 ($65), Ultra-96 ($250), and the Firefly-RK3399 ($200) boards. For the VTA hardware designs, we use an automated 8-bit integer scaling and translation pass from 32-bit floating-point (FP32) with negligible accuracy degradation. For our CPU baselines, we use the TVM autotuner to obtain FP32 CPU kernels that take advantage of NEON vectorization, multi-threading and state of the art scheduling tricks (spatial tiling, Winograd transform etc.). For our GPU baseline, we use the ARM CL v18.03 and exploit 16-bit floating-point (FP16) library support. ARM CL is missing support conv2d transpose for DCGANs, demonstrating VTA’s ability to stay ahead of the curve for unconventional workloads.

Figure 8 shows end-to-end results that can be discussed in two groups of comparable devices in terms of cost: (1) VTA on the Pynq vs. Cortex-A9 (sub-$100), and (2) VTA on Ultra96 vs. Cortex-A53 and Mali-T860 GPU ($200-$250). First, VTA on the Pynq-Z1 outperforms the Cortex-A9 CPU by , , and on MobileNet, ResNet-18, ResNet-34 and DCGAN. Second, VTA on the Ultra-96 outperforms the Cortex-A53 by , , , and on MobileNet, ResNet-18, ResNet-34, ResNet-50 and DCGAN. In addition, VTA on the Ultra-96 outperforms the mobile-class Mali-T860 GPU by , , and on MobileNet, ResNet-18, ResNet-34 and ResNet-50.

Overall, VTA demonstrates that the flexibility of the architecture can offer high performance while forming a evolutionary path forward for accelerating diverse workloads on various devices.

6 Conclusion

In this paper, we present hardware-software blueprint for “flexible specialization”: the idea that efficiency gains from hardware specialization is not mutually exclusive with workload flexibility. We present VTA, a parametrizable deep learning architecture that is explicitly programmed via a two-level ISA. We co-design the accelerator with a runtime system that JIT compiles micro-kernels to provide operational flexibility. With this approach, we support less conventional operators such as convolution transpose, and grouped convolutions without needing to apply changes to the hardware. We show in our evaluation that VTA can effectively target different FPGAs, multiple workloads, and leverage off the shelf deep learning compilers to quickly integrate optimized software with specialized hardware. Finally, we demonstrate that a well integrated hardware and software stack lets us perform full stack optimization and exploration on FPGAs.

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