Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
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We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5 reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5 optimum relative-timed RCA, iii) 32.9 respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5 optimum QDI early output CCLA, v) 14.2 respectively compared to an optimum QDI early output BCLARC, and vi) 12.2 11.6 output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.
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