PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

02/03/2023
by   Qiong Li, et al.
0

Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However, hardware implementation of posit arithmetic requires further exploration, especially for the dot-product operations dominated in deep neural networks (DNNs). It has been implemented by either the combination of multipliers and an adder tree or cascaded fused multiply-add units, leading to poor computational efficiency and excessive hardware overhead. To address this issue, we propose an open-source posit dot-product unit, namely PDPU, that facilitates resource-efficient and high-throughput dot-product hardware implementation. PDPU not only features the fused and mixed-precision architecture that eliminates redundant latency and hardware resources, but also has a fine-grained 6-stage pipeline, improving computational efficiency. A configurable PDPU generator is further developed to meet the diverse needs of various DNNs for computational accuracy. Experimental results evaluated under the 28nm CMOS process show that PDPU reduces area, latency, and power by up to 43 existing implementations. Hence, PDPU has great potential as the computing core of posit-based accelerators for deep learning applications.

READ FULL TEXT

page 1

page 3

research
07/07/2022

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores

Low-precision formats have recently driven major breakthroughs in neural...
research
01/27/2021

Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators

In this paper, we propose a mixed-precision convolution unit architectur...
research
12/20/2022

Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks

To keep up with the ever-growing performance demand of neural networks, ...
research
10/23/2020

Efficient Floating-Point Givens Rotation Unit

High-throughput QR decomposition is a key operation in many advanced sig...
research
04/04/2023

Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines

The acceleration of deep-learning kernels in hardware relies on matrix m...
research
04/03/2023

Monotonicity of Multi-Term Floating-Point Adders

In the literature on algorithms for performing the multi-term addition s...
research
08/07/2023

FPPU: Design and Implementation of a Pipelined Full Posit Processing Unit

By exploiting the modular RISC-V ISA this paper presents the customizati...

Please sign up or login with your details

Forgot password? Click here to reset