Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact

03/20/2018
by   Radhika Jagtap, et al.
0

Across applications, DRAM is a significant contributor to the overall system power, with the DRAM access energy per bit up to three orders of magnitude higher compared to on-chip memory accesses. To improve the power efficiency, DRAM technology incorporates multiple power-down modes, each with different trade-offs between achievable power savings and performance impact due to entry and exit delay requirements. Accurate modeling of these low power modes and entry and exit control is crucial to analyze the trade-offs across controller configurations and workloads with varied memory access characteristics. To address this, we integrate the power-down modes into the DRAM controller model in the open-source simulator gem5. This is the first publicly available full-system simulator with DRAM power-down modes, providing the research community a tool for DRAM power analysis for a breadth of use cases. We validate the power-down functionality with sweep tests, which trigger defined memory access characteristics. We further evaluate the model with real HPC workloads, illustrating the value of integrating low power functionality into a full system simulator.

READ FULL TEXT

page 3

page 5

page 6

research
08/18/2019

System Evaluation of the Intel Optane Byte-addressable NVM

Byte-addressable non-volatile memory (NVM) features high density, DRAM c...
research
09/02/2021

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

Repeated off-chip memory accesses to DRAM drive up operating power for d...
research
09/28/2022

Unveiling the Real Performance of LPDDR5 Memories

LPDDR5 is the latest low-power DRAM standard and expected to be used in ...
research
09/19/2014

Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power Management

Modern DRAM architectures allow a number of low-power states on individu...
research
08/19/2021

Monarch: A Durable Polymorphic Memory For Data Intensive Applications

3D die stacking has often been proposed to build large-scale DRAM-based ...
research
02/20/2019

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study

It has become increasingly difficult to understand the complex interacti...
research
04/22/2022

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers

This paper presents the design of AgilePkgC (APC): a new C-state archite...

Please sign up or login with your details

Forgot password? Click here to reset