GREENER: A Tool for Improving Energy Efficiency of Register Files

09/14/2017
by   Vishwesh Jatala, et al.
0

Graphics Processing Units (GPUs) maintain a large register file to increase thread block occupancy, hence to improve the thread level parallelism (TLP). However, register files in the GPU dissipate a significant portion of the total leakage power. Leakage power of the register file can be reduced by putting the registers into low power (SLEEP or OFF) state. However, one challenge in doing so is the lack of precise register access information for each instruction at run-time. This paper proposes GREENER (GPU REgister file ENErgy Reducer): a tool for minimizing leakage energy of the register file of GPUs. GREENER employs a compile-time analysis to estimate the run-time register access information. The result of the analysis is used to determine the power state of the registers (ON, SLEEP, or OFF) after each instruction. We propose a new power optimized assembly instruction format that allows GREENER to encode the power state of the registers with its instruction. Further, GREENER transforms a given input assembly language to a power optimized assembly. The optimized assembly, along with a run-time optimization to update the power state of a register during execution, results in significant power reduction. We implemented GREENER in GPGPU-Sim simulator and used GPUWattch framework to measure the leakage power of register file. We evaluated the effectiveness of GREENER on 21 kernels from CUDASDK, GPGPU-SIM, Parboil, and Rodinia benchmarks suites. We observe an average reduction of register leakage energy by 69.2 maximum reduction of 88.41 slowdown on average).

READ FULL TEXT
research
04/06/2023

Optimized Real-Time Assembly in a RISC Simulator

Simulators for the RISC-V instruction set architecture (ISA) are useful ...
research
05/09/2021

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU

The ever-increasing parallelism demand of General-Purpose Graphics Proce...
research
02/11/2023

Auto-SpMV: Automated Optimizing SpMV Kernels on GPU

Sparse matrix-vector multiplication (SpMV) is an essential linear algebr...
research
10/19/2020

Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation

Graphics Processing Units (GPUs) employ large register files to accommod...
research
06/10/2020

A GPU Register File using Static Data Compression

GPUs rely on large register files to unlock thread-level parallelism for...
research
04/30/2022

Predict; Do not React for Enabling Efficient Fine Grain DVFS in GPUs

With the continuous improvement of on-chip integrated voltage regulators...
research
04/08/2022

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

Pre-silicon side-channel leakage assessment is a useful tool to identify...

Please sign up or login with your details

Forgot password? Click here to reset