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Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case
Network-on-Chip (NoC) is currently the paradigm of choice to interconnec...
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Medium Access Control in Wireless Network-on-Chip: A Context Analysis
Wireless on-chip communication is a promising candidate to address the p...
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Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication
Ubiquitous multicore processors nowadays rely on an integrated packet-sw...
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A Review on Software Architectures for Heterogeneous Platforms
The increasing demands for computing performance have been a reality reg...
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Design Space Exploration of Power Delivery For Advanced Packaging Technologies
In this paper, a design space exploration of power delivery networks is ...
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CHIPKIT: An agile, reusable open-source framework for rapid test chip development
The current trend for domain-specific architectures (DSAs) has led to re...
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Architectural exploration of heterogeneous memory systems
Heterogeneous systems appear as a viable design alternative for the dark...
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Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors
The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly co-integrate multiple specialized processor and memory chiplets. In such data-hungry multi-chip architectures, current Networks-in-Package (NiPs) may not be enough to cater to their heterogeneous and fast-changing communication demands. This position paper makes the case for wireless in-package nanonetworking as the enabler of efficient and versatile wired-wireless interconnect fabrics for massive heterogeneous processors. To that end, the use of graphene-based antennas and transceivers with unique frequency-beam reconfigurability in the terahertz band is proposed. The feasibility of such a nanonetworking vision and the main research challenges towards its realization are analyzed from the technological, communications, and computer architecture perspectives.
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