Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing

06/03/2018
by   Satwik Patnaik, et al.
0

Here we advance the protection of split manufacturing (SM)-based layouts through the judicious and well-controlled handling of interconnects. Initially, we explore the cost-security trade-offs of SM, which are limiting its adoption. Aiming to resolve this issue, we propose effective and efficient strategies to lift nets to the BEOL. Towards this end, we design custom "elevating cells" which we also provide to the community. Further, we define and promote a new metric, Percentage of Netlist Recovery (PNR), which can quantify the resilience against gate-level theft of intellectual property (IP) in a manner more meaningful than established metrics. Our extensive experiments show that we outperform the recent protection schemes regarding security. For example, we reduce the correct connection rate to 0% for commonly considered benchmarks, which is a first in the literature. Besides, we induce reasonably low and controllable overheads on power, performance, and area (PPA). At the same time, we also help to lower the commercial cost incurred by SM.

READ FULL TEXT
research
03/07/2019

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

Split manufacturing was introduced as an effective countermeasure agains...
research
08/11/2019

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Split manufacturing (SM) and layout camouflaging (LC) are two promising ...
research
11/16/2018

Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs

With the globalization of manufacturing and supply chains, ensuring the ...
research
06/24/2018

Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL

Split manufacturing (SM) seeks to protect against piracy of intellectual...
research
10/26/2021

Exploring eFPGA-based Redaction for IP Protection

Recently, eFPGA-based redaction has been proposed as a promising solutio...
research
11/14/2017

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Layout camouflaging (LC) is a promising technique to protect chip design...
research
05/20/2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis

The globalization of the electronics supply chain is requiring effective...

Please sign up or login with your details

Forgot password? Click here to reset