An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder
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This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to overcome the problem of gate orphans associated with internal carry propagation. The relative-timing assumption is however independent of the RCA size. The primary benefits of the relative-timed RCA are processing of valid data incurs data-dependent forward latency, while the processing of spacer involves a very fast constant time reverse latency of just 1 full adder delay which represents the ultimate in the design of an asynchronous RCA with the fastest reset. The secondary benefits of the relative-timed RCA are it achieves good optimization of power and area metrics simultaneously. A 32-bit relative-timed RCA constructed using the proposed early output full adder achieves respective reductions in forward latency by 67 to the optimized strong-indication, weak-indication, and early output 32-bit asynchronous RCAs existing in the literature. Based on a similar comparison, the proposed 32-bit relative-timed RCA achieves corresponding reductions in cycle time by 83 relative-timed RCA occupies 27 strong-indication counterpart and 17 weak-indication counterpart, and features increased area occupancy by a meager 1 power dissipation of all the asynchronous 32-bit RCAs are found to be comparable since they all satisfy the monotonic cover constraint. The simulation results obtained correspond to a 32/28nm CMOS process.
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