
A/D Converter Architectures for EnergyEfficient Vision Processor
AI applications have emerged in current world. Among AI applications, co...
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Precise deep neural network computation on imprecise lowpower analog hardware
There is an urgent need for compact, fast, and powerefficient hardware ...
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Practical approach to programmable analog circuits with memristors
We suggest an approach to use memristors (resistors with memory) in prog...
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Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing
Temporal Neural Networks (TNNs) use time as a resource to represent and ...
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Demonstrating Advantages of Neuromorphic Computation: A Pilot Study
Neuromorphic devices represent an attempt to mimic aspects of the brain'...
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EnergyEfficient TimeDomain VectorbyMatrix Multiplier for Neurocomputing and Beyond
We propose an extremely energyefficient mixedsignal approach for perfo...
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Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses
Current large scale implementations of deep learning and data mining req...
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A Timedomain Analog Weightedsum Calculation Model for Extremely Low Power VLSI Implementation of Multilayer Neural Networks
A timedomain analog weightedsum calculation model is proposed based on an integrateandfiretype spiking neuron model. The proposed calculation model is applied to multilayer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation. We also propose very largescale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, the timedomain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. However, they have to use very high resistance devices on the order of GΩ. We designed a proofofconcept (PoC) CMOS VLSI chip to verify weightedsum operation with the same weights and evaluated it by postlayout circuit simulation using 250nm fabrication technology. High resistance operation was realized by using the subthreshold operation region of MOS transistors. Simulation results showed that energy efficiency for the weightedsum calculation was 290 TOPS/W, more than one order of magnitude higher than that in stateoftheart digital AI processors, even though the minimum width of interconnection used in the PoC chip was several times larger than that in such digital processors. If stateoftheart VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectricgate FETs is necessary.
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