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05/12/2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses
The performance and capacity of solid-state drives (SSDs) are continuous...
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01/12/2022
A simple model for citation curve
There is considerable interest in the citation count for an author's pub...
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02/02/2021
MANA: Microarchitecting an Instruction Prefetcher
L1 instruction (L1-I) cache misses are a source of performance bottlenec...
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12/30/2020
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling
Modern computing devices employ High-Bandwidth Memory (HBM) to meet thei...
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10/19/2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Graphics Processing Units (GPUs) employ large register files to accommod...
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09/01/2020
A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers
Data prefetching, i.e., the act of predicting application's future memor...
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05/04/2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
We empirically evaluate an undervolting technique, i.e., underscaling th...
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12/30/2018
ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning
Memory bandwidth bottleneck is a major challenges in processing machine ...
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09/24/2018
Die-Stacked DRAM: Memory, Cache, or MemCache?
Die-stacked DRAM is a promising solution for satisfying the ever-increas...
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08/15/2018
Making Belady-Inspired Replacement Policies More Effective Using Expected Hit Count
Memory-intensive workloads operate on massive amounts of data that canno...
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08/14/2018
Scale-Out Processors Energy Efficiency
Scale-out workloads like media streaming or Web search serve millions of...
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05/11/2018