Christian Pilato | DeepAI

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∙ 11/08/2022

Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization

Optimizing data movements is becoming one of the biggest challenges in h...

0 Stephanie Soldavini, et al. ∙

∙ 05/16/2022

ALICE: An Automatic Design Flow for eFPGA Redaction

Fabricating an integrated circuit is becoming unaffordable for many semi...

0 Chiara Muscari Tomajoli, et al. ∙

∙ 03/21/2022

Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics

Numerical simulations can help solve complex problems. Most of these alg...

0 Stephanie Soldavini, et al. ∙

∙ 03/10/2022

Designing ML-Resilient Locking at Register-Transfer Level

Various logic-locking schemes have been proposed to protect hardware fro...

0 Dominik Sisejkovic, et al. ∙

∙ 01/25/2022

HOLL: Program Synthesis for Higher OrderLogic Locking

Logic locking "hides" the functionality of a digital circuit to protect ...

0 Gourav Takhar, et al. ∙

∙ 11/08/2021

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction

Semiconductor design houses rely on third-party foundries to manufacture...

0 Jitendra Bhandari, et al. ∙

∙ 10/26/2021

Exploring eFPGA-based Redaction for IP Protection

Recently, eFPGA-based redaction has been proposed as a promising solutio...

0 Jitendra Bhandari, et al. ∙

∙ 08/19/2021

A Survey on Domain-Specific Memory Architectures

The never-ending demand for high performance and energy efficiency is pu...

0 Stephanie Soldavini, et al. ∙

∙ 08/06/2021

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics

Many applications are increasingly requiring numerical simulations for s...

0 Karl F. A. Friebel, et al. ∙

∙ 05/20/2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis

The globalization of the electronics supply chain is requiring effective...

0 Christian Pilato, et al. ∙

∙ 04/03/2021

Compiler Infrastructure for Specializing Domain-Specific Memory Templates

Specialized hardware accelerators are becoming important for more and mo...

0 Stephanie Soldavini, et al. ∙

∙ 04/03/2021

High-Level Synthesis of Security Properties via Software-Level Abstractions

High-level synthesis (HLS) is a key component for the hardware accelerat...

0 Christian Pilato, et al. ∙

∙ 03/06/2021

EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms

High-Performance Big Data Analytics (HPDA) applications are characterize...

0 Christian Pilato, et al. ∙

∙ 10/11/2020

ASSURE: RTL Locking Against an Untrusted Foundry

Semiconductor design companies are integrating proprietary intellectual ...

0 Christian Pilato, et al. ∙

∙ 09/02/2020

Agile SoC Development with Open ESP

ESP is an open-source research platform for heterogeneous SoC design. Th...

0 Paolo Mantovani, et al. ∙

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