Alex Kogan | DeepAI

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Featured Co-authors

Rachid Guerraoui
62 publications
Dave Dice
13 publications
Virendra J. Marathe
7 publications
Igor Zablotchi
6 publications
Tim Harris
4 publications
Shady Issa
3 publications
Yossi Lev
1 publication
David Dice
1 publication

∙ 01/12/2023

Improving Inference Performance of Machine Learning with the Divide-and-Conquer Principle

Many popular machine learning models scale poorly when deployed on CPUs....

0 Alex Kogan, et al. ∙

∙ 05/16/2021

Intra-process Caching and Reuse of Threads

Creating and destroying threads on modern Linux systems incurs high late...

0 Dave Dice, et al. ∙

∙ 05/14/2021

Ready When You Are: Efficient Condition Variables via Delegated Condition Evaluation

Multi-thread applications commonly utilize condition variables for commu...

0 Dave Dice, et al. ∙

∙ 02/12/2021

Optimizing Inference Performance of Transformers on CPUs

The Transformer architecture revolutionized the field of natural languag...

0 Dave Dice, et al. ∙

∙ 02/07/2021

Hemlock : Compact and Scalable Mutual Exclusion

We present Hemlock, a novel mutual exclusion locking algorithm that is e...

0 Dave Dice, et al. ∙

∙ 01/28/2021

Compact Java Monitors

For scope and context, the idea we'll describe below, Compact Java Monit...

0 Dave Dice, et al. ∙

∙ 08/06/2020

Efficient Multi-word Compare and Swap

Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool f...

0 Rachid Guerraoui, et al. ∙

∙ 06/22/2020

Scalable Range Locks for Scalable Address Spaces and Beyond

Range locks are a synchronization construct designed to provide concurre...

0 Alex Kogan, et al. ∙

∙ 03/10/2020

Fissile Locks

Classic test-and-test (TS) mutual exclusion locks are simple, and enjoy ...

0 Dave Dice, et al. ∙

∙ 05/26/2019

Avoiding Scalability Collapse by Restricting Concurrency

Saturated locks often degrade the performance of a multithreaded applica...

0 Dave Dice, et al. ∙

∙ 10/12/2018

Compact NUMA-Aware Locks

Modern multi-socket architectures exhibit non-uniform memory access (NUM...

0 Dave Dice, et al. ∙

∙ 10/03/2018

TWA – Ticket Locks Augmented with a Waiting Array

The classic ticket lock consists of ticket and grant fields. Arriving th...

0 Dave Dice, et al. ∙

∙ 10/03/2018

BRAVO – Biased Locking for Reader-Writer Locks

Designers of modern reader-writer locks confront a difficult trade-off r...

0 David Dice, et al. ∙

∙ 04/17/2015

The Influence of Malloc Placement on TSX Hardware Transactional Memory

The hardware transactional memory (HTM) implementation in Intel's i7-477...

0 Dave Dice, et al. ∙

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