The unifying principle behind all neuromorphic architectures lies in their attempt to emulate certain structural and dynamical aspects of biological nervous systems in order to inherit some of their well-known functional and metabolic advantages over conventional silicon substrates. However, precisely what these aspects are remains a holy grail of computational neuroscience, and our best attempts at answering this question are still rather conjectural. This state of active exploration is reflected by the broad diversity of the current neuromorphic landscape .
Consequently, our approach to neuromorphic engineering is explicitly geared towards building systems that can serve as scientific tools for studying this question. By adhering to a restricted set of biologically inspired principles, we enable an efficient implementation in silico with respect to both emulation speed and power consumption. Additionally, our proposed architecture emphasizes precision, scalability and, in particular, a substantial degree of flexibility. This relates not only to the wide-ranged configurability of neuro-synaptic parameters and connectivity, but most importantly to the ability of influencing our circuits during emulation, which goes significantly beyond synaptic plasticity, as outlined below.
In this manuscript, we describe the core principles underlying the BrainScaleS-2 architecture, followed by the emulation of a diverse set of spiking neural networks, which we have chosen to emphasize different aspects of the chip’s operation and capabilities, as well as different computational principles that we believe are relevant for biological information processing.
BrainScaleS-2 is a family of mixed-signal neuromorphic systems. It is centered around an analog neural network core implementing neuron and synapse circuits that behave similarly to their biological archetypes (Fig. 1).
The neurons  feature lif dynamics with synaptic currents modeled as superpositions of spike-triggered exponential kernels. The membrane is connected by a programmable conductance to a reset potential for a finite refractory period as soon as it crosses a certain threshold. Additional mechanisms such as neuronal adaptation and exponential near-threshold dynamics  or dendritic interaction  enable the emulation of more complex structure and dynamics. All neurons are individually configurable via an on-chip analog parameter memory  and a set of digital control values.
Voltages and currents are – scaled to utilize the available dynamic range – directly represented in the respective circuits and evolve in continuous time. Leveraging the intrinsic capacitances and conductances of the technology, time constants of neuron and synapse dynamics are rendered 1000 times smaller compared to typical values found in biology. This thousandfold acceleration facilitates the execution of time-consuming tasks, such as performing high-dimensional parameter sweeps, the investigation of learning and metalearning, or statistical computations requiring large volumes of data [6, 4].
Each neuron is associated with a column of synapse circuits , which receive their inputs from the chip’s digital backend. The synaptic weight is stored in local sram. It further holds a label, enabling synapses to filter afferent events tagged with their respective source address. Each synapse also implements an analog circuit for measuring pairwise correlations between pre- and post-synaptic spike events , enabling access to various forms of stdp. The analog correlation traces are accessible via cadc, which also allow the digitization of neuronal observables such as the membrane potential.
The versatility of the BrainScaleS-2 architecture is substantially augmented by the incorporation of freely programmable embedded microprocessors 
. Together with their simd vector units, which are tightly coupled to the synapse arrays’ sram controllers and the cadc, they form ppu for efficient control of synaptic plasticity. Access to the on-chip configuration bus further allows the processor to also reconfigure all other components of the neuromorphic system during experiment execution. The ppu can thus be used for a vast array of applications such as near-arbitrary learning rules, on-line circuit calibration, structural network reconfiguration, or the co-simulation of an environment capable of continuous interaction with the network running on the neuromorphic core.
Iii-a Deep learning using precise spike timing
In many applications, the time and energy to solution represent essential commodities. For spiking networks, optimal use of these resources often imposes to have as few and as early spikes as possible. However, the discrete nature of spikes makes it difficult to apply conventional machine learning algorithms based on differentiable loss functions.
In the time-to-first-spike coding scheme, a neuron encodes a continuous variable as the time elapsed before its first spike. The decision of a network performing a classification task is given by the first neuron to spike in the label layer (Fig. 2A,B). For such networks, an efficient gradient-descent-based learning scheme was first proposed in 
, using error backpropagation on a continuous function of output spike times.
We have generalized this method to include an exact, closed-form expression for finite membrane time constants [16, 15] and applied it to a 3-layer network emulated on BrainScaleS-2 (Fig. 2). The loss was calculated as the cross-entropy of a softmax function on negative spike times, in order to maximize the distance between correct and incorrect label layer spikes. Fig. 2D shows its evolution during training and the associated classification accuracy for a simple 4-class learning task (Fig. 2C). The evolution of the label neuron spike times for one example class is shown in Fig. 2E. The robustness of both the applied learning rule and the emulated network dynamics is evidenced by the clear separation of first-spike times.
A particularly appealing feature of this implementation is its extreme communication sparsity, with only one input spike per input variable and at most one spike per emulated neuron before classification. After learning, the emulated network needed less than
to classify an image. This duration scales proportionally to the chosen synaptic and membrane time constants, which in our case were set to. Taking into consideration relaxation times between patterns, our setup is able to handle a pattern throughput of at least , independently of emulated network size .
Iii-B Sampling-based Bayesian computation
In this quintessentially spike-based framework, neurons become stochastic due to background spiking input, thereby lending themselves to the representation of binary random variables: during post-spike refractoriness, a neuron is considered to be in the state , and otherwise (Fig. 3
A,B). With appropriate synaptic connections, the resulting network dynamics inherently generate a sequence of samples from the learned distribution. This enables the training of spiking networks to perform sampling-based Bayesian inference in arbitrary binary probability spaces, with applications to generative as well as discriminative problems[33, 23].
Contrastive Hebbian learning  was performed with the hardware in the loop, i.e., with updates being calculated on a host PC [36, 23]. Each training step was run for of hardware time, corresponding to bio time and approximately samples.
Training was monitored using the Kullback-Leibler divergence between sampled and target distribution (Fig. 3C). After training, the network reliably sampled from its target distribution and from associated conditional distributions (Bayesian inference, Fig. 3D). Compared to previous neuromorphic realizations of neural sampling with analog neurons [31, 23], the BrainScaleS-2 system allows unprecedented precision, while still enabling fast inference due to its thousandfold acceleration.
Iii-C Reinforcement learning
Recent advances in reinforcement learning have enabled artificial systems to achieve unprecedented performance in board and computer games. As a learning principle with clear roots in neurobiology, it is also of interest as a framework for neuromorphic agents to optimize their performance through repeated interaction with an environment.
Three-factor learning rules  can implement reinforcement learning in spiking neural networks using a global neuromodulator and local observables such as spike rates. As already shown in , the BrainScaleS-2 architecture supports the implementation of an R-STDP learning rule [12, 11] in a closed-loop setup contained fully on chip. Its application to a simplified version of the Pong video game is shown in Fig. 4A. The network dynamics were emulated by the neuromorphic substrate, while the embedded plasticity processor took on a dual role. First, it simulated the game dynamics, creating a host-independent setup. Second, it calculated the plasticity updates using the synaptically stored correlation traces according to , where is the reward, its moving average and an stdp-like eligibility trace.
During training, the network learned to keep the ball close to the middle of the paddle (Fig. 4B). Implicitly, the experiment also demonstrates how learning can compensate fixed-pattern noise in the analog neuro-synaptic circuits (Fig. 4C): while the excitability of uncalibrated neurons varied significantly due to mismatch effects, synapses that would negatively impact correct tracking of the ball were systematically depressed to a subthreshold strength with respect to their postsynaptic neuron. Furthermore, this setup demonstrates the speed and power advantages of the BrainScaleS-2 architecture compared to software simulations, as shown in Fig. 4D/E.
Iii-D Structural plasticity
Synaptic plasticity is well known to not only be limited to adjusting the strength of synapses; the connectome itself undergoes continuous change during the lifetime of an individual [20, 26, 21]. By constraining the number of expressed synapses to enforce a certain level of sparsity, the nervous system appears to manage its spatial and energetic budget . Similar constraints apply to all physical information-processing systems, with neuromorphic ones being no exception. In particular, the synaptic fan-in of silicon neurons is often limited.
We implemented a synaptic update policy that incorporates structural plasticity, enabling neurons to dynamically select a set of suitable synapses out of a pool of potential connections, that optimizes performance for a chosen task while maintaining a sparse connectome . The learning rule is composed of three parts: an stdp term that potentiates correlated connections, a homeostatic regularizer that limits post-synaptic firing rates and encourages synaptic competition, and a stochastic component that induces exploration. A pruning condition is executed periodically, removing synapses with a weight below a certain threshold and randomly reassigning them.
Structural plasticity is enabled by bundling presynaptic sources and injecting them into a single synapse row (Fig. 5A): as each synapse can only gate one of these to its home neuron, pruning and reassigning of a synapse is simply implemented by changing its label. The reconfiguration is thereby fully local and, in particular, does not involve time-consuming sorting of routing tables or connectivity lists . If bundles are disjoint, their size also effectively sets the synaptic sparsity to .
We applied the above algorithm to a supervised learning task, where the network was trained to classify the Iris data set. We randomly placed 48 receptor neurons on the two-dimensional feature plane spanned by petal width and length. The firing rate of a receptor was set to increase with its proximity to a presented data point. In three separate scenarios, the resulting input spike trains were injected into , , and synaptic rows, leading to three different levels of sparsity: each label neuron could only see , , and of the receptors at each point in time, respectively. During training, teacher stimuli ensured that the correct label neurons were excited when an input belonging to their respective class was presented.
The emulated plasticity rule led to self-organized reconfiguration of their receptive fields (Fig. 5B), as the correlation between teacher signal and receptor proximity to the presented data drove the potentiation of associated synaptic weights. For higher degrees of enforced sparsity, convergence times were longer, as the search for relevant inputs in the feature space became statistically more challenging. Ultimately however, the learning rule enabled the network to achieve near-perfect classification in all three scenarios (Fig. 5C), demonstrating its ability to ensure a better utilization of synaptic resources without prior knowledge of the input data.
Iii-E Insect navigation
Recent developments in biological imaging and data processing have facilitated unprecedented insight into numerous functional aspects of insect brains [5, 40, 39]. For example, it has been shown that a structure known as the central complex is involved in navigational behavior . Based on physiological data from the bee’s central complex and following , we emulated a network for path integration (Fig. 6A) that reproduces bees’ ability to return to their nest’s location after exploring the environment for sources of food.
Each experiment started with a spread-out phase, in which a virtual insect performed a random walk starting from a certain origin. During this phase, the modeled network had no effect on the insect motion but was only provided with the sensory data of the absolute head orientation and the optical flow field of a left and right eye. In the second part of the experiment, the return phase, the insect’s motion was determined by the motor neurons, which were part of the network. The insect’s head orientation was encoded by four spike sources that each represented a cardinal direction similar to a compass. The optical flow field was similarly represented by two spike generators that fired with a rate proportional to the optical flow as derived from the left and right eye, respectively (FL and FR). Moreover, the two motor neurons (ML and MR) steered the insect by providing propulsion on the left or right hand side, similar to a tank drive.
While the model in  comprises 90 fire-rate-neurons with floating-point precision, the network on BrainScaleS-2 achieved about the same functional performance with only 18 neurons. Additionally, we implemented the short-term memory mechanism employed by the integrator neurons to store directional distance as a synaptic mechanism.
The total flight duration was set to on the hardware, which corresponds to in biology. In that time, sensory information and steering signals were exchanged between body and brain every . During the first the insect performed a random outbound journey, after which it returned to the nest. Sample trajectories can be seen in Fig. 6B,C. The average spike rate of all neurons and spike generators was ( bio), which is in good agreement with experimental data from drosophila  or locusts .
In this experiment, the ppu handled multiple tasks: the processing of synaptic modulations for the integrator neurons, the simulation of the environment, an emulation of all sensors including the corresponding spike stimuli, the translation of neuronal data into actions of motion, and the entire experiment control. Apart from the setup and readout phase, the experiment ran entirely self-contained on the BrainScaleS-2 system.
Iv Discussion and outlook
In a post-Moore era, neuromorphic circuits represent a promising venue for advancing the computational capabilities of silicon. This manuscript motivates how, by coupling the advantages of analog circuits with the flexibility of general-purpose digital computation and control, our BrainScaleS-2 architecture contributes to the research-oriented territory of the neuromorphic landscape. In our endeavor, we share a common goal with other promising architectures such as  and , which follow radically different design paradigms with advantages and drawbacks of their own.
A key aspect that we do not address above, but ultimately decides the value of such systems for computational neuroscience research, is their scalability. Following integration concepts first proposed in  and studied in, e.g., [32, 36], the BrainScaleS-2 architecture is explicitly designed to scale up to large, multi-chip systems. These will conserve the network-size-independent speedup and energy efficiency that we have addressed in our above experiments, thus providing access to spiking network studies that are otherwise prohibitive for simulation software running on conventional substrates.
We gratefully acknowledge funding from the European Union under grant agreements 604102, 720270, 785907 (HBP) and the Manfred Stärk Foundation.
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