High throughput is one of the primary targets for the evolution of mobile communications. The next generation of mobile communication, i.e., 6G, is expected to supply Tbp/s throughput. which requires roughly a x increase in throughput over the 5G standards.
-coset codes, defined by Arıkan in , are a class of linear block codes with the generator matrix . is an binary matrix defined as , in which and denotes the -th Kronecker power of .
Polar codes is a specific type of -coset codes, adopted for the 5G control channel, respectively. The throughput of polar codes is limited by the successive cancellation (SC) decoders, since they are serial in nature.
Recently, a parallel decoding framework of -coset codes is proposed in . It is alternately decoded on two factor graphs and , as shown in Fig. 1. The permuted graph is generated by swapping the inner codes and outer codes. The decoder only decodes the inner codes of each graph . In each , the inner codes are independent sub-codes that can be decoded in parallel. The code construction under the parallel decoding algorithm is different from polar/RM codes, and is studied separately in .
I-B Motivations and Contributions
This paper introduce an ASIC implementation based on the parallel decoding framework (PDF). We set up a decoder which can support -coset codes. It deploys sub-decoder to decode the 128 independent sub-codes in parallel. The target of high throughput and area efficiency is decomposed into the reduction of sub-codes decoding latency, worst-case iteration time, and chip area, and optimized respectively.
We adopt the proposal in  which employs successive cancellation (SC) decoders as the component decoder. It can support soft-in-hard-out decoding which results in low decoding complexity and reduced interconnection among the component decoders. In this work, we propose hardware-oriented optimizations on LLR generation and quantization. We implemented the whole decoder in hardware and present the ASIC layout to evaluate multiple key metrics. The hardware-specific data is obtained from the cells flip ratio from the circuit simulation results and the parasitic capacitance extracted from the layout result. With process, the area efficiency is , the power consumption is and energy efficiency is around . Scaled to , the area efficiency can reach with five iterations.
Ii Parallel Decoding
A parallel decoding framework is introduced in , where three types of component decoders (i) soft-output SC list (SCL), (ii) soft-output SC permutation list and (iii) soft cancellation (SCAN) are employed to decode the sub-codes (inner codes). To achieve even higher area efficiency, this work adopts SC , i.e., without list decoding, as the sub-decoder. In this section, we describe the parallel decoding framework-successive cancellation (PDF-SC) algorithm from the implementation point of view.
Ii-a Parallel decoding framework (PDF)
We use to denote the -th code bit position of -th inner sub-code, and to denote the code bit position in the -coset code. They have the following relationship
The aforementioned parallel turbo-like decoding framework is described in Algorithm 1. In every two iterations, the algorithm alternately decodes the two graphs and (line 4 in Algorithm 1) with inner component decoders. The -th component decoder, denoted by , is a SC decoder assisted by the error detector.
Note that each component decoder takes a soft input vector
, but outputs hard code bit estimatesand error detecting results . The mismatch between soft input and hard output poses a challenge for iterative decoding, since the SC component decoders in the next iteration cannot directly take the hard output from the previous iteration as input. To solve this problem,  proposes to generate soft values from the hard outputs. Specifically, the log likelihood ratio (LLR) of the -th code bit in the -th iteration, denoted by , is calculated from the hard decoder outputs from the alternate graph (line 5).
For the -th component decoder, the hard output vector and soft input vector have length
and the error detection indicator is a binary value.
The independent inner sub-codes allow us to instantiate component decoders for maximum degree of parallelism. After iterations, the algorithm outputs all hard bits.
Ii-B Component decoder:
The component decoder  is described in Algorithm 2. Before each SC decoding, error detection is performed. This can be achieved by applying a syndrome check based on hard decisions (line 25 in Algorithm 2). The cases with detected errors are denoted by Type-1 and otherwise Type-2.
The error detector brings two-fold advantages. On the one hand, since Type- component codes require no further SC decoding, this approach reduces power consumption. If all sub-codes pass error detection, decoding can be early terminated for further power saving. On the other hand, the error detection result provides us with additional information that the input LLRs of Type-2 component codes are more reliable than those of Type-1. Such information can be used to improve the overall performance by estimating the input LLRs from the hard outputs.
Ii-C Input LLR generator:
In each iteration, the input LLRs are calculated by
Since SC decoder is invariant to input LLR scaling, we can cancel noise varianceduring LLR initialization. By multiplying both sides of (2) and (3) by , the equations are simplified as follows
where and is the received signal.
We use a pair of new coefficients to replace and :
in which is determined by the binary and the hard outputs of the previous two iterations as in (6). The input signal calculation reduces to only one addition operation.
Iii An ASIC implementation
In this section, we present the ASIC implementation of a PDF-SC decoder in TSMC process for . The hardware optimization addresses both the SC decoders for component codes and the overall parallel decoding framework for -coset codes.
Iii-a Bit Quantization
Lower precision quantization is the key to higher throughput, thanks to its reduced implementation area and increased clock frequency. As a tradeoff, performance loss is expected. To maximize throughput while retaining performance, we must determine an appropriate quantization width. Specifically, we use simulation to find out the smallest quantization width of a fixed-point decoder within performance loss from a floating decoder.
First, we compare the performance of component codes under Algorithm 2. We test two cases and with different quantization widths. According to Fig.2, 6-bit quantization achieves the same performance as floating-point, 5-bit quantization incurs loss, and 4-bits quantization yields significant loss. Therefore, we set the quantization width to 5 or 6 bits.
We then simulate the BLER performance of the long codes and under different quantizations, as shown in Fig. 3. Similarly, 6-bit quantization has no performance loss, and 5-bit quantization only incurs loss for both code rates. Again, 4-bit quantization suffers from performance degradation.
Iii-B SC Core Optimization
A component SC decoder is optimized via Rate-0 nodes, Rate-1 nodes, single parity check (SPC) nodes and repetition nodes (REP). The decoder skips all Rate-0 nodes, parallelizes Rate-1, SPC and REP nodes for code blocks shorter than 32. If neither applies, maximum-likelihood (ML) multi-bit decision  is employed for 4-bit blocks.
The architecture of SC decoders used here is described in , with supported code length reduced from 32768 to 128 to save area. With TSMC technology, an SC core synthesizes to 4,100 area. Under 1.05 clock frequency, its latency is shown in Table I.
Iii-C SC Core Sharing
A unique design that significantly reduces area is called “SC core sharing”. In particular, we bind four SC cores as a sub-decoder group. The four SC cores share input/output pins, LLR updating circuits and error detector related components. The sharing reduces a lot of local computation resources and global routing resources, but increases the latency between iterations. However, the overall area efficiency and power efficiency are improved.
In addition, we reuse the adders in the SC core to perform the input LLR addition in (5). These adders were used for the -function calculation in each processing element (PE) . Altogether, area can be saved for each sub-decoder group. Fig. 4 shows the architecture of a sub-decoder group, including how adders in the PEs are reused. We run the synthesis flow with TSMC process, and the resulting area of a sub-decoder group is 19,400.
Iii-D Global Layout
Combining all algorithmic and hardware optimizations, the synthesized decoder ASIC requires area. The global layout is presented in Fig. 5. In the center of the layout is the top logic, including the input channel LLR storage, finite state machine (FSM) controller, interleaved connection routing and output buffer. The aforementioned 32 sub-decoder groups (SG in the figure) are placed around the top logic, highlighted by different colors.
Iv Key Performance Indicators
|Info||Iter-||Es/N||Latency||Area Eff.||Convert to|
|Implementation||This Work||This Work||This Work||This Work|||||||||
|List size / Iterations||5||8||5||8||1||1||8||8|
|Technology||All in TSMC|
The key performance indicators (KPIs) are examined. First of all, we evaluate the area efficiency using equation 111The error detector can early terminate the decoding, but its worst-case latency is guaranteed by maximum iteration times, as required by most practical communication systems.. The proposed decoder can reach up to hundreds of gigabits per second within one square millimeter. The evaluated throughput in given in Table II222The third column “Es/N0” is chosen such that BLER.. With TSMC process, the area efficiency for code rate and are and when the maximum number of iterations is eight. If we reduce to five iterations by allowing performance loss, the area efficiency can reach and . The estimated throughput under and technologies can be converted from 333The converting ratios including cell density ratio and speed improvement ratio are obtained from the TSMC process introductions [10, 11].. With the more advanced process, the throughput is as high as and , which are much higher than the target given in the EPIC project . Note that the KPI is achieved at code length , which exhibits significant coding gain over codes with length . With future technologies of and below, it is promising to achieve an extremely challenging target of .
The area efficiency is also compared with a highly-optimized and fabricated ASIC polar444The polar codes are constructed by Gaussian approximation at Es/N0=, , and for ()=(), (), () and () respectively. is code length and is code rate. decoder in . For both code rates, the throughput of the proposed decoder (with five iterations) is nine times as fast as a polar fast-SC decoder, and 53 times that of a CA-SC-List-8 decoder555In , the fabricated ASIC SC decoder supports code length .. Detailed comparison results can be found in Table III.
We further evaluate the average running time and power consumption (per packet). In the lower SNR region, longer decoding time and higher power consumption are observed. But in the higher SNR region, both decoding time and power consumption are much smaller, thanks to the built-in error detection and early termination function described in section II-B. Specifically, only 15% component codes cannot pass the error detection while the rest 85% can skip SC decoding. The power consumption (mW/mm) and energy efficiency (pJ/bit) follow similar trend to the average running time. When Es/N0, the power consumption is smaller than . The energy efficiency is around , again meeting the target proposed in . These results666Note that the power consumption with eight iterations is lower than that with five iterations. This is due to the lower error detection successful rate during the first five (1-5) iterations. The last three (5-8) iterations consume much lower power, which reduced the averaged power level. are plotted in Fig. 6. The power consumption and energy efficiency are evaluated with TSMC process.
In this paper, we present an ASIC implementation of high-throughput -coset codes. The parallel decoding framework leads to a hardware with high area efficiency and low decoding power consumption. An area efficiency of is achieved within approximately process. The power consumption is as low as and energy efficiency is around . Scaled to process, the area efficiency can reach . It confirms that -coset codes can meet the high-throughput demand in next-generation wireless communication systems.
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