Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity

01/28/2022

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by   Fatemeh Sheikh Shoaei, et al.

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This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100 proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5 multiplier.