Ternary circuits: why R=3 is not the Optimal Radix for Computation

by   Daniel Etiemble, et al.

A demonstration that e=2.718 rounded to 3 is the best radix for computation is disproved. The MOSFET-like CNTFET technology is used to compare inverters, Nand, adders, multipliers, D Flip-Flops and SRAM cells. The transistor count ratio between ternary and binary circuits is generally greater than the log(3)/log(2) information ratio. The only exceptions concern a circuit approach that combines two circuit drawbacks (an additional power supply and a circuit conflict between transistors) and only when it implements circuits based on the ternary inverter. For arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones using the same technology.



There are no comments yet.


page 1

page 2

page 3

page 4


Multivalued circuits and Interconnect issues

Many papers have presented multi-valued circuits in various technologies...

The Mind Grows Circuits

There is a vast supply of prior art that study models for mental process...

Exact, complete expressions for the thermodynamic costs of circuits

Common engineered systems implement computations using circuits, as do m...

Comparing ternary and binary adders and multipliers

While many papers have proposed implementations of ternary adders and te...

Some Results on the Power of Nondeterministic Computation

In this paper, we consider the power of nondeterministic computation in ...

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

Generators of arithmetic circuits can automatically deliver various impl...

Comparing quaternary and binary multipliers

We compare the implementation of a 8x8 bit multiplier with two different...
This week in AI

Get the week's most popular data science and artificial intelligence research sent straight to your inbox every Saturday.

I Introduction

Multivalued circuits have been studied for more than fifty years. Many ternary and 4-valued circuits have been proposed using different integrated circuit technologies. Two main arguments have been used to justify these proposals:

  • For computation, radix R = 3 would be more economical than R = 2 because the “optimal” radix would be R = e = 2.718, according to a demonstration presented in [1]. It was the motivation for the ternary circuits and more specifically the Russian Setun Ternary Computer developed in 1958 at Moscow State University [2]. The same argument can be found in many proposals of ternary circuits. A typical quote is: “The most efficient multiple-valued system, which leads to the least product cost and complexity, is ternary logic" [3].

  • Multivalued circuits having more logical states, more information could be transmitted through wires, reducing the amount of interconnections inside and outside a chip. This second argument can be found in nearly every proposal of m-valued circuits. We just present one among a lot of similar quotes: “One of the main problems in binary logic is the high volume of interconnections which can increase the chip area and power consumption" [4].

We are faced to a significant contradiction. The ternary radix is supposed to be the most efficient one. However, digital electronics is based on binary circuits. For more than 40 years, the doubling of the number of transistors every N months (12, then 18, then 24) according to Moore’s law has been realized by regularly launching a new generation of CMOS technologies, called a technological node. The different successive nodes are shown in Figure 1. If Moore’s law is slowing, 7-nm nodes were already used in 2018 and next ones are announced.

Fig. 1: CMOS technological nodes

The interconnection argument raises another question. It is quite evident that ternary operators have less input and output connections than the corresponding binary ones. The reduction factor corresponds to log(3)/log(2) = 1.58, which is the ratio between information transmitted by ternary and binary wires. Typical values are shown in Table I. For 64 bits, there are 36% less wires with ternary operators. However, the reduced wire count is only applicable for the input and output wires of the considered ternary operators, whatever operator is considered: gate, adder, multiplier, and so on. What about the number of internal wires to interconnect the transistors that are used to implement the gate, adder or multiplier? Similarly, implementing a 64-bit carry propagate adder needs 64 1-bit adders, while a 41-trit adder only needs 41 1-trit adder. However, the 1-trit ternary adder is efficient only if its hardware complexity is no more than x1.58 the binary adder complexity. This complexity includes the number of transistors, the chip area, the power dissipation, the overall number of interconnects, propagation delays, etc.

Number of bits 8 16 32 64
Number of trits 5 11 21 41
TABLE I: Number of ternary and binary wires

In this paper, we discuss the first argument: R = e (3) as the optimal one. Then, we compare the relative complexity between ternary and binary operators.

Ii Refuting the Hurst demonstration

Ii-a The Hurst demonstration [1]

The number of digits necessary to express a range of N is given by N=, where R is the radix and d the number of digits, rounded to the next highest value. It is assumed that the complexity C of the system hardware is proportional to the digit capacity where k is a constant.


Differentiating with respect to R shows that R = e for a minimum cost C.

Fig. 2 shows that the curve complexity = f(R) for radixes 2 to 16 presents a minimum close to R = 3. Figure 3 is a zoom of Figure 2 for R = 2 to 4.

Fig. 2: Hardware complexity for Radixes 2 to 16

Fig. 3: Hardware complexity for Radixes 2 to 4

Fig. 3 leads to two different remarks:

  • There is a minimum value for R = e, but the curve is very flat. while and . The difference between C(2) and C(3) is 5.66%. Is such a difference sufficient to claim that ternary circuits are more efficient than binary ones?

  • It turns out that C(2) = C(4). Does binary circuits and quaternary circuits carrying the same amount of information have the same hardware complexity? It is very easy to find 4-valued circuits that are far more complex than the two corresponding binary ones. Such an example is provided below.

Ii-B A comparison of two binary inverters with one 4-valued inverter

Fig. 4 presents a 4-valued CNTFET inverter that has been presented in Microelectronics Journal in 2015 [5]. At that point in the discussion, there is no need to give details on the CNTFET technology as we compare transistor counts in the same technology. A 4-valued inverter carries 2 bits of information. Two binary inverters also carry 2 bits of information and use transistors. The 4-valued inverter has 10 transistors. The 4-valued inverter has 10/4 = x2.5 more transistors. Looking carefully to Fig. 4, we can observe that two binary inverters are included in the right part of the figure, which means that transistors T1 to T6 are the overhead of the 4-valued approach over the binary one! More, the 4-valued inverter needs three voltage supplies ( , and ) while the binary inverter only uses one. Many other examples could be provided with different technologies and different circuit styles. This result is not surprising. The binary values 00, 01, 10 and 11 are organized according to the Boolean lattice: each binary inverter has only one threshold level. The quaternary values are totally ordered: and the 4-valued inverter has 3 threshold levels. The number of threshold levels affects the hardware complexity.

Fig. 4: A 4-valued CNTFET inverter

Ii-C Refining Hardware System complexity

The problem with equation 1 is that the system cost is only considered proportional to the digit capacity , implicitly assuming that the hardware cost is the same for any value of R, which obviously is not true as previously shown. Let’s assume that the hardware complexity is proportional to , i.e. the number of threshold levels. The new equation is:


Fig. 5: New hardware system complexity

Fig. 5 presents the curve C=f(R) corresponding to Equation 2. Now, there is no minimal value. C=f(R) is continuously rising and the optimal radix is 2. Again, this result is not surprising. It corresponds to what has been observed with the tremendous story of binary integrated circuits for more than five decades.

Iii Comparing ternary and binary circuits in the same technology

Iii-a Methodology

Hardware complexity is difficult to define as many parameters can be considered:

  • Number of transistors

  • Number of interconnections

  • Chip area

  • Power dissipation

  • Propagation delays

  • Etc.

Obviously, the most significant information is the chip area and power dissipation of fabricated chips in a given technology. However, comparing ternary and binary circuits according to chip area and power dissipation is quite impossible as there are very few or no integrated ternary circuits available for comparisons.

So comparisons must be done with a simple criterion that is available from the circuit electrical scheme. We use the number of transistors. Although the transistor count is only an estimation, it gives significant insights. In fact, when using the same technology to implement the same operator, it is very doubtful that:

  • More transistors lead to less interconnects

  • More transistors lead to less chip area

  • More transistors lead to less power dissipation

When the difference in transistor counts is limited to a few %, no conclusion can be derived. However, if the transistor count for ternary circuits is x2, x3 or more than for binary circuits when the information ratio , it only means that the ternary circuits have more interconnects, more chip area, more power dissipation than the corresponding binary ones and are worthless. Figure 4 was a good example.

Iii-B Using CNTFET technology for comparing ternary and binary circuits

A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that uses a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET. The MOSFET-like CNTFETs having p and n types look the most promising ones. This technology has advantages and drawbacks:

  • CNTFET have variable threshold voltages (according to the inverse function of the diameter). Among advantages, high electron mobility, high current density, high transductance can be quoted.

  • Lifetime issues, reliability issues, difficulties in mass production and production costs are quoted as disadvantages.

We use this technology for several reasons:

  • This technology is one of the few proposed ones to overcome the limitations of the FinFET technologies after the end of Moore’s law.

  • The MOSFET-like CNTFETs have the same circuit styles than the CMOS technologies, which means that the comparison results are not limited to that technology.

  • A large number of CNTFET ternary or m-valued circuits have been proposed in the recent last years. We will use these proposals for the comparisons.

Iv Transistor counts for ternary and binary operators

The comparison is done at different levels:

  • Gate level: inverters, Nor and Nand gates

  • Arithmetic circuits such as adders and multipliers.

  • Sequential circuits: D latch and D flip-flop

  • Static memory cell

At each level, the transistor count ratio is compared with the information ratio (1.58).

Iv-a Inverters and basic gates

Ternary inverters and logic gates have three logical levels 0, 1 and 2. Voltage levels 0, and can be associated with the logical levels. It should be outlined that the voltage levels of the corresponding binary circuits are 0 and as power dissipation requires to use the minimal power supply voltage. It is obvious that 0 and 2 correspond to ground (0) and . For level 1, there are two possibilities: using one more power supply ( ) or getting a voltage through a resistor divider. The first option needs one additional power supply. The second one introduces a static power dissipation as a current flows from to ground.

  • Left part of Fig. 6 presents a ternary inverter [5] with an additional power supply. The level 1 is implemented by transistors T3, P4 and gates 1 and 2 when T1 and T2 are off.

  • Right part of Fig. 6 presents a ternary inverter [6] using a resistor divider. The level 1 is implemented by transistors N1, N3, P1, P3 when N2 and P2 are off. Paper [7] presents a similar CNTFET inverter.

  • Middle part of Fig. 6 presents a ternary inverter [8]. The level 1 is implemented by N2 when N1 and P1 are off. This inverter has only 3 transistors. However, with an additional power supply and an always ON transistor, it combines the drawbacks of the two previous inverters.

The corresponding binary inverter only uses two transistors. Table II gives the transistor count and ratio for ternary and binary inverters. We can observe that the 3T inverter [8] is the only one for which the 1.5 transistor ratio is smaller than the 1.58 information ratio. The difference is small and don’t counterbalance the two quoted drawbacks: additional power supply and dc current flow.

Fig. 6: Ternary inverters proposed in [5], [8], [6]
[5] [6] [8] bin
Transistor count 8 6 3 2
Transistor ratio 4 3 1.5 1
TABLE II: Transistor count for ternary and binary inverters

Fig. 7 presents the 2-input ternary Nand gates proposed in [5] and [6] . In both cases, the corresponding 2-input Nand gate has only four transistors. The 2-input ternary Nand corresponding to the 3-transistor inverter would only add the ON transistor to the usual Nand scheme. Table III gives the transistor count and ratio for 2-input and N-input ternary and binary Nands. Due to the duality between Nand and Nor gates, the results for Nor gates is exactly the same. In the left part of Fig. 7, we can observe that the ternary Nand gate includes one binary Nand gate, one binary Nor gate + two inverters. In the right part of Fig. 7, we can observe that the 2-input ternary Nand includes two Nand inverters + the two middle transistors that are needed for the level. Only the third approach [8] keeps a transistor count advantage over binary Nands.

Fig. 7: 2-input Nand gates proposed in [5] and [6]
Nb inputs [5] [6] [8] bin [5]/bin [6]/bin [8]/bin
 2 16 10 5 4 4 2.5 1.25
N 6N 4N+2 2N+1 2N 3 2+1/N 1+1/2N
TABLE III: Transistor count for ternary and binary Nand gates

Iv-B Adders

To profit from the reduced number of inputs and outputs, the ternary adder complexity should not be greater than x1.58 the complexity of the binary adder. We consider binary 1-bit and ternary 1-trit adders as they are the building block of any type of adder, from carry-propagate ones to more complicated ones.

Iv-B1 Binary and Ternary Hall adders

Unfortunately, ternary half adders cannot be implemented just by using Nand, Nor and inverter gates. While ternary basic logic gates can be derived from the binary gates by adding circuitry to implement the “middle" level, this approach can no longer be used when the truth table is more complicated than the basic gate truth tables. The truth table of a ternary half adder is given in Tab IV.

a b s cout
0 0 0 0
0 1 1 0
0 2 2 0
1 0 1 0
1 1 2 0
1 2 0 1
2 0 2 0
2 1 0 1
2 2 1 1
TABLE IV: Truth table of a ternary half adder

Fig. 8: General scheme of m-valued circuits.
A A1 A0
0 2 0 2 0
1 2 0 0 2
2 0 2 0 2
TABLE V: Truth table for ternary to binary decoder
2 2 0
0 2 1
0 0 2
TABLE VI: Truth table for the binary to ternary encoder

To implement an arbitrary truth table, the computation process obeys to the general scheme of m-valued circuits (Fig. 8) that was presented in [9]. The decoder truth table is given in Table V. The binary outputs of the decoder circuits are 0 and 2. From this table, we derive the following information:

  • when .

  • when .

  • when .

In the remaining part of this paper, we consider the approach that is used by references [6] and [7]. The encoder circuit uses 6 transistors instead of 3 with the 3-transistor inverter approach. While the transistor counts could be slightly greater, the difference is not significant, as the binary part in Fig. 8 always uses most of the transistors. The decoder and encoder circuits used in [7] are shown in Fig. 9. Part (a) corresponds to the threshold detector and . The CNT diameters of T1 and T2 set up the threshold for the first inverter while the second T3-T4 inverter is a normal binary inverter. Similarly, part (b) present the threshold detection between 0 and . Part (c) of the figure presents the binary to ternary encoder, which behaviour is shown in Table VI. In this table, the inputs are named and as in [7].

For the ternary full adder presented in [7], the binary equations are thus:


The corresponding circuit generating and is presented in Fig. 10. The carry generation is presented in Fig. 11. The generation of the carry output is decomposed into two parts. The first one delivers the binary carry output with levels 0 and . However, the ternary carry output has only 0 and 1 logical values. This means that a special carry encoder is needed that is shown in the part (b) of the figure.

The overall ternary half adder has a total of 16 + 16 + 16 + 6 + 12 = 66 transistors

Fig. 9: Decoder and encoder circuits [7].

Fig. 10: Sum binary parts.

Fig. 11: Carry generation.

Fig. 12: Binary half adders.

Fig. 13: CNTFET 3T Xor

There are different possible implementations of a binary half adder. A first one is presented in the left part of Fig 12 : it only uses Nand gates and one inverter. A second one is presented in the right part of Fig 12 : it is the typical implementation using a Xor gate that can be implemented with 3 transistors as proposed in [10] (Fig.13). It should be outlined that the 3T Xor like any circuitry using pass transistors doesn’t restore levels with the corresponding potential drawbacks: noise margins and propagation delays due to the series of pass transistors. The transistor counts of the ternary and binary versions are given in Table VII together with the transistor ratios between ternary and binary versions.

3-HA 2-HA without Xor 2- HA with Xor
Counts 66 18 9
Ratio 3/2 1 1/3.67 1/7.3
TABLE VII: Transistor counts and ratios for ternary and binary half adders

Iv-B2 Binary and Ternary Full adders

cin=0 cin=1
a b s0 cout0 a b s1 cout1
0 0 0 0 0 0 1 0
0 1 1 0 0 1 2 0
0 2 2 0 0 2 0 1
1 0 1 0 1 0 2 0
1 1 2 0 1 1 0 1
1 2 0 1 1 2 1 1
2 0 2 0 2 0 0 1
2 1 0 1 2 1 1 1
2 2 1 1 2 2 2 1
TABLE VIII: Truth table of a ternary full adder

The truth table of a ternary full adder is presented in TableVIII. The simpliest way to implement it is to generate sum10 and sum20 when cin=0 (left part of Table VIII) and sum11 and sum21 when cin=1 (right part of Table VIII). It turns out that sum21=sum10 (equation 1). The only additional computations are sum11 and cm1, plus the multiplexers to get , and according to cin. The different logical equations are:


The multiplexers correspond to the following equations:


Table IX summarizes the number of transistors needed to implement the different functions. The total number of transistors of the ternary full adder is thus 66+ 58 = 124.

function gate transistor count
inverter 2
sum11 complex gate 20
cm1 complex gate 12
complex gate 8
complex gate 8
complex gate 8
total 58
TABLE IX: Number of of additional transistors from half adder to full adder

Fig 14 presents two typical implementations of a full adder. The left only uses Nand gates. The right part uses Xor and Nand gates. A CNTFET 8T full adder (Fig 15) has been presented [10]. Again, this adder doesn’t restore levels and using it could raise issues. The transistor counts of the ternary and binary versions are given in Table X together with the transistor ratio between ternary and binary versions.

3-FA Nand 2-FA Xor 2-FA 8T 2-FA
Counts 124 36 18 8
Ratio 3/2 1 1/3.45 1/6.9 1/15.5
TABLE X: Transistor counts and ratios for ternary and binary full adders

Obviously, the estimation of propagation delays is more difficult without simulations. A rough comparison can be done. For the most conservative version of the binary adder (left part of Fig. 14, the critical path is a series of 6 2-input Nand gates. Except for the last gate, every Nand fan-out is 1. For the ternary adder, the critical path is a series of the following items:

  • 2 inverters for the decoder. The outputs of the decoder are heavily loaded by the different complex gates ( and ).

  • a complex gate : or or or . With a large number of transistors, any of these complex gates has a propagation delay far greater than a 2-input Nand gate.

  • a complex gate that implements a multiplexer: or or

  • the sum or carry final encoder circuits. The sum encoder is probably the critical one.

It is pretty sure that the ternary full adder propagation delay is significantly greater than the propagation delay of any version of the binary full adders.

Fig. 14: Binary full adders

Fig. 15: 8T binary full adder

Even with the most conservative implementation of the 1-bit adder, the 1-trit adder has more than x1.58 transistors than the 1-bit adder. A P-trit carry propagate adder is thus more complex that a N-bit carry propagate adder with .

Iv-C Ternary and Binary Multipliers

The truth table of a 1-trit multiplier is given in Table XI.

a b s cout
0 0 0 0
0 1 0 0
0 2 0 0
1 0 0 0
1 1 1 0
1 2 2 0
2 0 0 0
2 1 2 0
2 2 1 1
TABLE XI: Truth table of a one trit multiplier

Using the same approach as for the adder, the equations are:


The number of transistors is 4 (decoder)+ 12 (S1) + 12 (S2) + 6 (s encoder) + 4 (cout encoder) = 38.

The binary 1-bit multiplier is a And gate, which means 6 transistors (2-nput nand gate + inverter). The ratio is 6.3. One can observe that the 1-bit multiplier has 2 input and 1 output, while the 1-trit multiplier has 2 inputs and 2 outputs. This is a curious situation as m-valued logic is supposed to reduce the number of interconnections!

As for adders, comparing N-bit binary and P-trit ternary multipliers is interesting. We only make the comparison for N=8 and P=5. As a matter of fact, while , which means that the ternary multiplier has slightly less computational capability than the binary one. The comparison includes two parts:

  • the set of 1-bit and 1-trit multipliers.

  • the tree to reduce the set of partial products into a final sum of two reduced partial products. The Wallace tree is one of the possible reduction tree.

A 8x8 bit multiplier uses 1-bit multiplier while a 5x5 trit multiplier only use 1-trit multipliers. The ratio is . Obviously, this value is close to . However, the binary multiplier generates 8 partial products, while the ternary multiplier generates 10 partial products, 5 ternary ones and 5 binary ones provided by the ternary output and the binary carry output of each 1-trit multiplier. To benefit from the smaller number of 1-trit multiplier, its complexity should not be greater than x2.56 the complexity of the 1-bit multiplier, which is not the case with the 6.3 ratio that was computed.

Fig. 16: Wallace trees for 5x5 ternary (left) and 8x8 binary (right) multipliers

Fig. 16 compares the Wallace trees for the ternary and the binary multiplies. The left part presents the 5-stage ternary tree. 3 and 2 corresponds to the ternary and binary values. Ternary half and full adders are respectively showed with blue and yellow colors. The right part presents the 4-stage binary tree. Binary half and full adders also use blue and yellow colors.

The ternary Wallace tree uses 35 T-FAs and 7 T-HAs. When using a carry-propagate adder (CPA) for the final addition, the overall count is 38 T-FAs and 8 T-HAs. The binary Wallace tree uses 38 B-FAs and 15 B-HAs. When using CPA for the final addition,the overall count is 47 B-FAs and 17 B-HAs. So, the binary multiplier use 1.24 x more FAs and 2.12 x more HAs. However these ratios are too small to compensate the huge complexity disadvantage of the T-FAs and T-HAs compared to the binary ones.

The 5x5 ternary multiplier uses 6190 transistors versus 2382 for the 8x8 binary ones, i.e. x2.6 more transistors.

Radix 1-digit X HA FA Total
Binary 6 18 36 384 306 1692 2382
Ternary 38 66 124 950 528 4712 6190
TABLE XII: Transistor counts for 8x8 binary multiplier versus 5x5 ternary one

Iv-D Flip Flops and Memory Cells

The D-Flip is the most important flip-flop from which any other one could be derived. Fig. 17 presents a typical ternary D master slave flip flop. It corresponds directly to the binary D Flip Flop by replacing the binary inverters by ternary inverters. Table XIII gives the transistor counts for the different ternary and binary D Flip-Flops. Again, only the 3-transistor inverter approach has a transistor ratio less than the 1.58 information ratio.

Fig. 17: Ternary D-Flip-Flop
[5] [6] [8] bin
 Trans. count 40 32 20 16
Trans. ratio 2.5 2 1.25 1
TABLE XIII: Comparison of Ternary and Binary D-Flip Flops

SRAMs use static cells. There are several possible implementations of the memory cell. We consider the simplest ternary cell derived from the classical 6-T binary cell (Fig. 18). Table XIV gives the transistor counts for the different ternary and binary SRAM cells. Again, only the 3-transistor inverter approach has a transistor ratio less than the 1.58 information ratio.

Fig. 18: Ternary Memory Cell from [8]
[6] [8] bin
 Trans. count 14 8 6
Trans. ratio 2.33 1.33 1
TABLE XIV: Comparison of Ternary and Binary SRAM Cells

While Flip-Flops and Static Rams are based on the logic gates that are used to implement combinational operators, Dynamic Rams are based on electrical features instead of logical ones. Binary DRAMs use electrical charges to store bits in 1.5 T cells (1 transistor + 1 capacitance). M-valued SRAMs and DRAMs have been fabricated and tested by industrial companies in the 80’s and the 90’s, such as Hitachi [12], NEC [13] and [14], etc. They are detailed in [11]. During the following decades, there was no longer such presentations by industrial companies.

M-Valued flash memories also use similar techniques and were presented in the 90s [15, 16]. They are now largely used. 4-valued (MLC) flash memories store two bits per cell. 8-valued (TLC) memories store 3 bits per cell. In 2018, ADATA, Intel, Micron, and Samsung have launched some SSD products using QLD NAND-memory with 4 bits per cell. While binary flash memories have the advantage of faster write speeds, lower power consumption and higher cell endurance, M-valued flash memories provide higher data density and lower costs. These M-valued circuits (M=) are used for higher density, not for higher speeds.

V Conclusion

While the tremendous story of binary circuits for more than five decades is the best refutation of the supposed advantage of ternary circuits over binary ones, we have provided a refutation of the demonstration e=2.718 as the best radix for computation.

Ternary circuits have a log(3)/log(2) = 1.58 information advantage over binary circuits. However, ternary circuits would be interested if (and only if) their complexity in terms of gate count, interconnection count, chip area, propagation delay, etc. is no more than x1.58 the complexity of the corresponding binary circuits. Using MOSFET-like CNTFET circuits for comparing binary and ternary circuits, we have shown that this condition is fulfilled only in one specific case with two conditions:

  • when implementing the “middle" level by an ON transistor [8]. This approach uses two power supplies instead of one, and is electrical debatable: there is a dc path and a fight between two transistors for the lower level.

  • when implementing the basic gates (inverter, nand, nor, etc.) or the circuits based on the ternary inverter such as the D Flip-Flop and the SRAM cell.

For all the other ternary implementations and for the typical arithmetic circuits such as adders and multipliers, the ternary circuits are outperformed by the binary ones. Ternary circuits cannot avoid using two debatable techniques: either using one additional power supply adding to interconnection issues, or generating the “middle" level via a dc current flow which introduces static power dissipation.

It does not mean that ternary circuits can never be used: they can be used when they implement some functions having 3 different states. A good example is the ternary content-addressable memories (CAM) which cells store three different states: 0, 1 and X (don’t care). It allows to search for words having unknown and non-significant bits. However, faced to the still continuing advances of binary circuits, ternary circuits have been and will probably remain restricted to a small niche [17].


  • [1] S.L. Hurst, “Multiple-Valued Logic - Its Status and Its Future“, IEEE Trans. on Computers, VOL. C-33, No 12, December 1984.
  • [2] N. P. Brousentsov, S. P. Maslov , J. Ramil Alvarez, E.A. Zhogolev, “Development of ternary computers at Moscow State University", Russian Virtual Computer Museum, http://www.computer-museum.ru/english/setun.htm.
  • [3] S. Rezaie, R.F.Mirzaee, K. Navi and O. Hashemipour, “New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources", in Int. J. High Performance Systems Architecture, Vol. 5, No 3, 2015.
  • [4] M. Shahangian, S.A. Hosseini, S.H.Pishgar Komleh, “Design of a Multi-digit Binary-to-Ternary Converters Based on CNTFETs", in Circuits, Systems and Signal Processing, https://doi.org/10.1007/s00034-018-0977-3
  • [5] F. Sharifi, et al., “Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach”, Microelectronic. J (2015), http://dx.doi.org/10;1016/j.mejo.2015.09;018.
  • [6] S. Lin, Y-B. Yin and F. Lombardi, “CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuit", IEEE Transactions on Nanotechnology, Vol 10, No2, March 2011.
  • [7] S.K. Sahoo, G.Akhilesh, R. Sahoo and M. Mugkilar, “High Performance Ternary Adder using CNTFET", IEEE Transactions on Nanotechnology, Vol 16, No3, January 2017
  • [8] K. You and K. Nepal, “Design of a ternary static memory cell using carbon nanotube based transistors", in Micro and Nano Letters July 2011
  • [9] D.Etiemble and M.Israel, “Comparison of binary and multivalued integrated circuits according to VLSI criteria”, IEEE Computer, pp.28-42, April 1988.
  • [10] K.K. Nehru, T. Nagarjuna and G. Vijay, “Comparative Analysis of CNTFET and CMOS Logic Based Arithmetic Logic Unit", in Journal of Nano and Electronic Physics 9 (4), January 2017
  • [11] G. Gulak, “A review of multiple-valued memory technology”, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic, Fukuoka, 1998, pp. 222-231.
  • [12] M. Aoki et al, “A 16-level/Cell Dynamic Memory”, IEEE J. Solid State Circuits, Vol. SC-22, No 2, pp. 297-299, April 1987.
  • [13] T. Sugibayashi, I. Naritake, A. Utsugi et al, “A 1 Gb DRAM for File Application”, ISSCC Digest of Technical Papers, pp. 254-255, Feb. 1995.
  • [14] T. Murotani et al., “A 4-level Storage 4Gb DRAM”, ISSCC Digest of Technical Papers, pp.74-75, Feb. 1997.
  • [15] J. Bauer et al, “A multilevel-Cell 32Mb Flash Memory”, ISSCC Digest of Technical Papers, pp.132-133, Feb. 1995.
  • [16] T. Jung et al, ”A 3.3 V 128 Mb Multi-Level Flash Memory for Mass Storage Applications”, ISSCC Digest of Technical Papers, pp.32-33, Feb. 1996.
  • [17] D. Etiemble, Why M-Valued Circuits are restricted to a Small Niche”, in Journal of Multiple Valued Logic and Soft Computing, Vol. 9, No1, 2003.