Synthesizing Compact Hardware for Accelerating Inference from Physical Signals in Sensors

02/04/2020
by   Vasileios Tsoutsouras, et al.
0

We present dimensional circuit synthesis, a new method for generating digital logic circuits that improve the efficiency of training and inference of machine learning models from sensor data. The hardware accelerators that the method generates are compact enough (a few thousand gates) to allow integration within low-cost miniaturized sensor integrated circuits, right next to the sensor transducer. The method takes as input a description of physical properties of relevant signals in the sensor transduction process and generates as output a Verilog register transfer level (RTL) description for a circuit that computes low-level features that exploit the units of measure of the signals in the system. We implement dimensional circuit synthesis as a backend to the compiler for Newton, a language for describing physical systems. We evaluate the backend implementation and the hardware it generates, on descriptions of 7 physical systems. The results show that our implementation of dimensional circuit synthesis generates circuits of as little as 1662 logic cells / 1239 gates for the systems we evaluate. We synthesize the designs generated by the dimensional circuit synthesis compilation backend for a low-power miniature FPGA targeted by its manufacturer at sensor interface applications. The circuits which the method generated use as little as 27 dissipation of the FPGA's isolated core supply rail and show that, driven with a pseudorandom signal input stream, the synthesized designs use as little as 1.0 mW and no more than 5.8 mW. These results show the feasibility of integrating physics-inspired machine learning methods within low-cost miniaturized sensor integrated circuits, right next to the sensor transducer.

READ FULL TEXT

page 1

page 3

research
11/12/2018

Newton: A Language for Describing Physics

This article introduces Newton, a specification language for notating th...
research
02/28/2023

Tiny Classifier Circuits: Evolving Accelerators for Tabular Data

A typical machine learning (ML) development cycle for edge computing is ...
research
05/22/2023

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search

Logic synthesis is the first and most vital step in chip design. This st...
research
12/06/2020

MeLPUF: Memory in Logic PUF

Physical Unclonable Functions (PUFs) are used for securing electronic de...
research
10/29/2022

Neural Combinatorial Logic Circuit Synthesis from Input-Output Examples

We propose a novel, fully explainable neural approach to synthesis of co...
research
01/25/2021

ProbLock: Probability-based Logic Locking

Integrated circuit (IC) piracy and overproduction are serious issues tha...
research
09/16/2020

Probabilistic Value-Deviation-Bounded Source-Dependent Bit-Level Channel Adaptation for Approximate Communication

Computing systems that can tolerate effects of errors in their communica...

Please sign up or login with your details

Forgot password? Click here to reset