Log In Sign Up

Synchronizing Deterministic Push-Down Automata Can Be Really Hard

by   Henning Fernau, et al.

The question if a deterministic finite automaton admits a software reset in the form of a so-called synchronizing word can be answered in polynomial time. In this paper, we extend this algorithmic question to deterministic automata beyond finite automata. We prove that the question of synchronizability becomes undecidable even when looking at deterministic one-counter automata. This is also true for another classical mild extension of regularity, namely that of deterministic one-turn push-down automata. However, when we combine both restrictions, we arrive at scenarios with a PSPACE-complete (and hence decidable) synchronizability problem. Likewise, we arrive at a decidable synchronizability problem for (partially) blind deterministic counter automata. There are several interpretations of what synchronizability should mean for deterministic push-down automata. This is depending on the role of the stack: should it be empty on synchronization, should it be always the same or is it arbitrary? For the automata classes studied in this paper, the complexity or decidability status of the synchronizability problem is mostly independent of this technicality, but we also discuss one class of automata where this makes a difference.


page 1

page 2

page 3

page 4


Synchronization of Deterministic Visibly Push-Down Automata

We generalize the concept of synchronizing words for finite automata, wh...

The Emptiness Problem for Valence Automata over Graph Monoids

This work studies which storage mechanisms in automata permit decidabili...

Lecture Notes on Automata, Languages, and Grammars

These lecture notes are intended as a supplement to Moore and Mertens' T...

Bisimilarity in fresh-register automata

Register automata are a basic model of computation over infinite alphabe...

Counter Machines and Distributed Automata: A Story about Exchanging Space and Time

We prove the equivalence of two classes of counter machines and one clas...

On the decomposition of generalized semiautomata

Semi-automata are abstractions of electronic devices that are determinis...

1 Introduction

The classical synchronization problem asks, for a given deterministic finite automaton (DFA), if there exists a synchronizing word, i.e., an input that brings all states of the automaton to a single state. While this problem is solvable in polynomial time [cerny1964, Vol2008, San2005], many variants, such as synchronizing only a subset of states [San2005], or synchronizing only into a specified subset of states [DBLP:journals/ipl/Rystsov83], or synchronizing a partial automaton without taking an undefined transition [DBLP:journals/mst/Martyugin14], are PSPACE-complete. Restricting the length of a potential synchronizing word of some DFA by an integer parameter in the input also yields a harder problem, namely the NP-complete short synchronizing word problem [Rys80, DBLP:journals/siamcomp/Eppstein90]. The field of synchronizing automata has been intensively studied over the last years also in attempt to verify the famous Černý conjecture, claiming that every synchronizable DFA admits a synchronizing word of quadratic length in the number of states [cerny1964, DBLP:journals/jalc/Cerny19, DBLP:journals/eik/Starke66b, DBLP:journals/jalc/Starke19]. We are far from solving this combinatorial question, as the currently best upper bound on this length is only cubic [DBLP:journals/jalc/Shitov19, DBLP:conf/stacs/Szykula18]. For more on synchronization of DFAs and the Černý conjecture, we refer to the surveys [Vol2008, beal_perrin_2016, JALC20].

The idea of bringing an automaton to a well-defined state by reading a word, starting from any state, can be seen as implementing a software reset. This is why a synchronizing word is also sometimes called a reset word. But this very idea is obviously not restricted to finite automata. In this work, we want to move away from deterministic finite automata to more general deterministic push-down automata. What should a synchronizing word mean in this context? Mikami and Yamakami first studied in [MY20] three different models, depending on requirements of the stack contents when a word  drives the automaton into a synchronizing state, irrespectively of the state where processing  started: we could require at the end (a) that the stack is always empty; or (b) that the stack contents is always the same (but not necessarily empty); or (c) that the stack contents is completely irrelevant upon entering the synchronizing state. They demonstrated in [MY20] some upper and lower bounds on the maximum length of the shortest synchronizing word for those three models of push-down automata, dependent on the stack height. Here, we study these three models from a complexity-theoretic perspective. However, as we show in our first main result, synchronizability becomes undecidable when asking about synchronizability in any of the stack models. Clearly, by restricting the length of a potential synchronizing word of some DPDA by an integer parameter (given in unary), we can observe that the corresponding synchronization problems all become NP-complete, as the hardness is trivially inherited from what is known about DFA synchronizability. Therefore, we will not consider such length-bounded problem variants any further in this paper. Yet, it remains interesting to observe that with DFAs, introducing a length bound on the synchronizing word means an increase of complexity, while for DPDAs, this introduction means dropping from undecidability close to feasibility. Beside general DPDAs, we will study these stack model variants of synchronization for sub-classes of DPDAs such as deterministic counter automata (DCA), deterministic (partially) blind automata and finite-turn variants of DPDAs and DCAs. In [vpda-crossref], further restricted sub-classes of DPDAs, such as visibly and very visibly deterministic push-down and counter automata are considered. There, all considered cases are in EXPTIME and even membership in P and PSPACE is observed, contrasting our undecidability results here.

Closest to the problems studied in our paper comes the work of Chistikov et al. [DBLP:journals/jalc/ChistikovMS19] reviewed in the following, as their automaton model could be viewed as a special case of push-down automata, related to input-driven pushdown automata [DBLP:conf/icalp/Mehlhorn80] which later became popular as visibly push-down automata [DBLP:conf/stoc/AlurM04]. In [DBLP:journals/jalc/ChistikovMS19], the synchronization problem for so-called nested word automata (NWA) has been studied, where the concept of synchronization has been generalized to bringing all states to one single state such that for all runs the stack is empty (or in its start configuration) after reading the synchronizing word. In this setting the synchronization problem is solvable in polynomial time, whereas the short synchronizing word problem is PSPACE-complete (here, the length bound is given in binary) and the question of synchronizing from or into a subset is EXPTIME-complete.

The DFA synchronization problem has been generalized in the literature to other automata models including infinite-state systems with infinite branching such as weighted and timed automata [DBLP:conf/fsttcs/0001JLMS14, DBLP:phd/hal/Shirmohammadi14] or register automata [babari2016synchronizing]. For instance, register automata are infinite state systems where a state consists of a control state and register contents. A synchronizing word for a register automaton brings all (infinitely many) states to the same state (and same register content). The synchronization problem for deterministic register automata (DRA) is PSPACE-complete and NLOGSPACE-complete for DRAs with only one register.

Finally, we want to mention that the term synchronization of push-down automata has already some occurrences in the literature, i.e., in  [caucal2006synchronization, DBLP:journals/mst/ArenasBL11], but here the term synchronization refers to some relation of the input symbols to the stack behavior [caucal2006synchronization] or to reading different words in parallel [DBLP:journals/mst/ArenasBL11] and is not to be confused with our notion of synchronizing states.

We are presenting an overview on our results at the end of the next section, where we introduce our notions more formally.

2 Definitions

We refer to the empty word as . For a finite alphabet we denote with the set of all words over and with the set of all non-empty words. For we set . For we denote with the length of , with for the ’th symbol of , and with for the factor of . We call a prefix and a suffix of . The reversal of is denoted by , i.e., for , .

We call a deterministic finite automaton (DFA for short) if is a finite set of states, is a finite input alphabet, is a transition function , is the initial state and is the set of final states. The transition function is generalized to words by for . A word is accepted by if and the language accepted by is defined by . We extend to sets of states or to sets of letters , letting . Similarly, we may write to define for each . The synchronization problem for DFAs (called DFA-Sync) asks for a given DFA whether there exists a synchronizing word for . A word is called a synchronizing word for a DFA if it brings all states of the automaton to one single states, i.e., .

We call a deterministic push-down automaton (DPDA for short) if is a finite set of states; the finite sets and are the input and stack alphabet, respectively; is a transition function ; is the initial state; is the stack bottom symbol which is only allowed as the first (lowest) symbol in the stack, i.e., if and contains , then only occurs in as its prefix and moreover, ; and is the set of final states. We will only consider real-time push-down automata and forbid -transitions, as can be seen in the definition. Notice that the bottom symbol can be removed, but then the computation gets stuck.

Following [DBLP:journals/jalc/ChistikovMS19], a configuration of is a tuple . For a letter and a stack content with we write if . This means that the top of the stack is the right end of . We also denote with the reflexive transitive closure of the union of over all letters in . The input words on top of are concatenated accordingly, so that . The language accepted by a DPDA is . We call the sequence of configurations the run induced by , starting in , and ending in . We might also call the final state of the run.

We will discuss three different concepts of synchronizing DPDAs. For all concepts we demand that a synchronizing word maps all states, starting with an empty stack, to the same synchronizing state, i.e., for all . In other words, for a synchronizing word all runs started on some states in end up in the same final state. In addition to synchronizing the states of a DPDA we will consider the following two conditions for the stack content: (1) , (2) . We will call (1) the empty stack model and (2) the same stack model. In the third case, we do not put any restrictions on the stack content and call this the arbitrary stack model.

As we are only interested in synchronizing a DPDA, we can neglect the start and final states.

As mentioned above, we will show that synchronizability of DPDAs is undecidable, which is in stark contrast to the situation with DFAs, where this problem is solvable in polynomial time. Hence, it is interesting to discuss deterministic variants of classical sub-classes of context-free languages. In this paper, we focus on one-counter languages and on linear languages and related classes. A deterministic (one) counter automaton (DCA) is a DPDA where . Note that our DCAs can perform zero-tests by checking if the bottom-of-stack symbol is on top of the stack. As we will see that also with this restriction, synchronizability is still undecidable, we further restrict them to the partially blind setting [greibach1978blind]. This means in our formalization that a transition either satisfies , or is a prefix of , i.e., , and then both (for ) and . The situation is even more delicate with one-turn or, more general, finite-turn DPDAs, whose further discussion and formal definition we defer to the specific section below.

We are now ready to define a family of synchronization problems, the complexity of which will be our subject of study in the following chapters. [Sync-DPDA-Empty]  
Given: DPDA .
Question: Does there exist a word that synchronizes in the empty stack model?
For the same stack model, we refer to the synchronization problem above as Sync-DPDA-Same and as Sync-DPDA-Arb in the arbitrary stack model. Variants of these problems are defined by replacing the DPDA in the definition above by a DCA, a deterministic partially blind counter automaton (DPBCA), or by adding turn restrictions, in particular, whether the automaton is allowed to make zero or one turns of its stack movement.

Outlook and summary of the paper

We summarize our results in Table 1. In short, while already seemingly innocuous extensions of finite automata (with counters or with 1-turn push-downs) result in an undecidable synchronizability problem, some extensions do offer some algorithmic synchronizability checks, although nothing efficient. At the end, we show how to apply some of our techniques to synchronizability questions concerning sequential transducers.

class of automata/problem empty stack model same stack model arbitrary stack model
DPDA undecidable undecidable undecidable
1-Turn-Sync-DPDA undecidable undecidable undecidable
0-Turn-Sync-DPDA PSPACE-complete undecidable PSPACE-complete
DCA undecidable undecidable undecidable
1-Turn-Sync-DCA PSPACE-complete PSPACE-complete PSPACE-complete
0-Turn-Sync-DCA PSPACE-complete PSPACE-complete PSPACE-complete
DPBCA decidable decidable decidable
Table 1: Complexity status of the synchronization problem for different classes of deterministic real-time push-down automata in different stack synchronization modes as well as finite-turn variants of the respective synchronization problem.

As an auxiliary result for proving undecidability of finding 1-turn synchronizing words for real-time deterministic push-down automata, we also prove undecidability of the inclusion and intersection non-emptiness problems for these automata, which could be an interesting result on its own. We also showcase how a variant of DFA synchronization, called DFA-Sync-From-Into-Subset, is useful to prove membership in PSPACE. As with this type of problems, these membership proofs are sometimes technical, this could be helpful in similar settings. To understand this problem, first look at the following one, called Global Inclusion Problem for Non-Initial Automata in [DBLP:journals/ipl/Rystsov83]: [DFA-Sync-Into-Subset (PSPACE-complete, see Theorem 2.1 in [DBLP:journals/ipl/Rystsov83])]  
Given: DFA , subset .
Question: Is there a word such that ? [DFA-Sync-From-Into-Subset]  
Given: DFA , subsets .
Question: Is there a word such that ?

Using the previously mentioned PSPACE-hardness and adapting a subset construction as in [San2005, Theorem 1.22], which then boils down to a reachability problem, one can show: DFA-Sync-From-Into-Subset is PSPACE-complete.

The reader can find proofs for this and several other assertions in the appendix of this paper.

3 General DCAs and DPDAs: When Synchronizability is Really Hard

The inclusion problem for deterministic real-time one counter automata that can perform zero-tests is undecidable [10.1007/978-3-642-22993-0_20, minsky1961recursive]. This result is used to prove undecidability of synchronization in any general setting as the main result of this section. However, there are special cases of DPDAs and DCAs that have a decidable inclusion problem (see [DBLP:journals/ieicet/HiguchiWT95] as an example) so that this argument does not apply to these sub-classes. We will have a closer look at some of these sub-classes in the following sections. The problems Sync-DCA-Empty, Sync-DCA-Same, and Sync-DCA-Arb are undecidable.


We give a reduction from the undecidable intersection non-emptiness problem for real-time DCAs [10.1007/978-3-642-22993-0_20]. Let and be two DCAs over the same input alphabet with disjoint state sets. We construct a DCA , where we neglect start and final states, which is synchronizable in the empty stack model if and only if the DCAs and accept a common word. The same construction also works for the same stack and arbitrary stack models. We assume and . For the states in and , the transition function agrees with and for all letters in . In the following, let . For , we set and . Further, for we set and . For , we set and . For , we set with all other transitions we stay in and increase the counter. Hence, the state can only be left with an empty counter and this is only the case if no letter other than has been read before. For the state , we set , and .

First, assume there is a word . Then, the word synchronizes all states of the DCA into the state . Let be stack contents such that and . Let . Then synchronizes in the empty stack model.

For the other direction assume there exists a word that synchronizes in the empty stack model. The states and forces since otherwise these states cannot be left. Since the state has no outgoing transition, it must be our synchronizing state. In order to reach it, must contain at least one letter . Let be an index such that and for , . With a letter we move from all final states to the state and from all non-final states of and we go to a state and increase the counter. As we cannot leave the states if we reach them once with a non-empty counter, reading a from a non-final state causes the automaton to reach a configuration from which we no longer can synchronize the automaton. Hence, we know that after reading all active states are in the set . Let be an index with with such that for , . Then is a word which is accepted by both DCAs and .

It is easy to see that clearing the stacks in state is not crucial and hence the reduction also works for the same stack and arbitrary stack models. ∎

The problems Sync-DPDA-Empty, Sync-DPDA-Same, and Sync-DPDA-Arb are undecidable.∎

How can we overcome the problem that, even for deterministic one-counter languages, the synchronizability problem is undecidable? One of the famous further restrictions are (partially) blind counters, to which we turn our attention next.

4 Partially Blind Deterministic Counter Automata

The blind and partially blind variations of counter automata have been introduced by Greibach in [greibach1978blind]

. She already noticed that the emptiness problem for such automata (even with multiple counters) is decidable should the reachability problem for vector addition systems, also known as Petri nets, be decidable, which has been proven some years later

[Mayr1981reachability, Kosaraju1982reachability]; its non-elementary complexity has only been recently fully understood [czerwinskietal2019reachability]. Although we will stick to the models introduced so far in the following statements and proofs, we want to make explicit that our decidability results also hold for deterministic multi-counter automata. But as we focus on discussing families of automata describing languages between regular and context-free, we refrain from giving further details here.

Because partially blind counters can simulate blind counters, our results hold for blind counters as well, but we make them explicit only for the partially blind case. One formal reason is that we want to preserve our stack model, while it becomes awkward to formalize blind counters in this stack model (see Appendix).

Recall that a partially blind counter automaton will get blocked when its counter gets below zero. The blindness refers to the fact that such a machine can never explicitly test its counter for zero. This translates into our formalization by requiring that a transition either means that or is a prefix of , i.e., , and then both (for ) and , i.e., the processing will somehow perform the same action, irrespectively of the stack contents, whenever this is possible; however, the machine will stop if it is trying to pop the bottom-of-stack symbol. As a specialty, such automata accept when having arrived in a final state together with having zero in its counter. We call a deterministic partially blind (one-)counter automaton a DPBCA.

The problems Sync-DPBCA-Empty, Sync-DPBCA-Same, and Sync-DPBCA-Arb are decidable.

We are not specifying the complexity here, but only mention that we are using, in the end, the reachability problem for Petri nets, which is known to be decidable, but only with a non-elementary complexity; see [Mayr1981reachability, Kosaraju1982reachability, czerwinskietal2019reachability]. However, we leave it as an open question if the synchronization complexity of DPBCAs is non-elementary. When looking into this question more in details, the number of states of the counter automaton could be a useful parameter to be discussed, as it influences the number of counters of the partially blind multi-counter automaton that we construct in our proof in order to show the claimed decidability result.


Let be some DPBCA. Let us first describe the case Sync-DPBCA-Empty. Here, we can first produce the multi-counter -fold product automaton from that starts, assuming , in the state . Notice that has many states and operates many counters. We could take as the set of final states . This mimicks state synchronization of : any word that synchronizes all states of will drive into . As mentioned above, partially blind multi-counter automata accept with final states and empty stacks, so that is synchronizable in the empty stack model if and only if accepts any word.

For the arbitrary stack model, we have to count down (removing  from any of the the stacks sequentially) until the bottom-of-stack symbol appears on all stacks on top (at the same time), leading to the variant . These are moves without reading the input (or reading arbitrary symbols at the end, this way only prolonging a possibly synchronizing word), but this does not matter, as the emptiness problem is decidable for partially blind nondeterministic multi-counter automata. It should be clear that accepts any word if and only if is synchronizable. For the case Sync-DPBCA-Same, the counting down at the end should be performed in parallel for all counters instead. ∎

5 Finite-Turn DPDAs

Finite-turn PDAs are introduced in [ginsburg1966finite]. From the formal language side, it is known that one-turn PDAs characterize the rather familiar family of linear context-free languages, usually defined via grammars. In our setting, the automata view is more interesting. We adopt the definition in [valiant1973decision]. For a DPDA an upstroke of is a sequence of configurations induced by an input word such that no transition decreases the stack-height. Accordingly a downstroke of is a sequence of configurations in which no transition increases the stack-height. A stroke is either an upstroke or downstroke. Note that exchanging the top symbol of the stack is allowed in both an up- and downstroke. A DPDA is an -turn DPDA if for all the sequence of configurations induced by can be split into at most strokes. Especially, for 1-turn DPDAs each sequence of configurations induced by an accepting word consists of one upstroke followed by a most one downstroke. There are two subtleties when translating this concept to synchronization: (a) there is no initial state so that there is no way to associate a stroke counter to a state, and (b) there is no language of accepted words that restricts the set of words on which the number of strokes should be limited. We therefore generalize the concept of finite-turn DPDAs to finite-turn synchronization for DPDAs in the following way, which offers quite an interesting complexity landscape. -Turn-Sync-DPDA-Empty  
Given: DPDA .
Question: Is there a synchronizing word in the empty stack model, such that for all states , the sequence of configurations consists of at most strokes? We call such a synchronizing word an -turn synchronizing word for . We define -Turn-Sync-DPDA-Same and -Turn-Sync-DPDA-Arb accordingly for the same stack and arbitrary stack models. Further, we extend the problem definition to real-time DCAs.

Motivated by the proof of Theorem 3, we are first reviewing the status of the inclusion problem for 1-turn DPDAs in the literature.

The inclusion problem for 1-turn DPDAs with -transitions is undecidable [DBLP:journals/tcs/Friedman76, valiant1973decision]. The intersection non-emptiness problem for real-time 1-turn non-deterministic push-down automata is also undecidable [DBLP:journals/tcs/Kim11a]. The decidability of the inclusion and intersection non-emptiness problems for real-time 1-turn deterministic push-down automata have not been settled in the literature; we will do so below by proving undecidability for both problems. We will present a reduction from the undecidable Post Correspondence Problem (PCP for short) [Pos46] to the intersection non-emptiness for real-time 1-turn DPDAs which also implies undecidability of the inclusion problem for this class since it is closed under complement. [PCP]  
Given: Two lists of input words over : , .
Question: Is there a sequence of indices with for such that ?

Observe that already Post stated this problem over binary alphabets. Much later, Matyasevich and Sénizergues [MatSen2005] showed that indeed lists of length seven are sufficient for undecidability. This was recently lowered to lists of length five by Neary [DBLP:conf/stacs/Neary15].

Let and be two real-time 1-turn DPDAs. Then the following problems are undecidable: Is ? Is ?


Let , be an instance of PCP. We construct from a real-time 1-turn DPDA where are marked numbers from 1 to . The set contains the start state , the states , and , and the single final state . The rest of is a partition into state sets such that the (deterministic partial) sub-automaton induced by reads the string and thereby pushes each symbol of on the stack, whereas symbols of the string leave the stack content unchanged. The sub-automaton induced by is embedded into , and thereby completed, by taking the state after reading to with the symbol . We go from and to the initial state of the sub-automaton induced by by the letter . With the letter the state maps to . Here, if the input symbol equals the symbol on top of the stack, we pop the stack and stay in until we reach the bottom symbol , in which case an additional letter  brings us to the final state . If the input symbol does not equal the symbol on top of the state we go to which is a trap state for all letters. Every other not yet defined transition on maps to the state . If not stated otherwise, every transition leaves the stack content unchanged.

For the list we construct a real-time 1-turn DPDA in a similar way except that here we push the strings on the stack and symbols of strings leave the stack unchanged.

The languages accepted by and are the following ones:

Obviously, the given PCP has a solution if and only if .

By complementing the set of final states, from one would arrive at a real-time 1-turn DPDA such that is the complement of , so that the given PCP has no solution if and only if . ∎

We will now adapt the presented construction to show that the synchronization problem for real-time one-turn DPDAs is undecidable in all three synchronization models.

1-Turn-Sync-DPDA-Empty, 1-Turn-Sync-DPDA-Same, and 1-Turn-Sync-DPDA-Arb are undecidable.


Let and be the real-time 1-turn DPDAs from the proof in Theorem 5. We take these machines as inputs for the construction in the proof of Theorem 3 to obtain the DPDA . Therefore, observe that the construction also works if the input machines are general DPDAs and not only DCAs. Further, observe that for and , if for both machines the only active state is the final state, then the stack of all runs is empty and hence the stack need not be altered in the synchronizing state and all transitions here can act as the identity and leave the stack unchanged.

If is a word in , then synchronizes in the empty, same, and arbitrary stack models; further is a 1-turn synchronizing word for . Conversely, if  is a 1-turn synchronizing word for , then must be of the form or where and is a word that does not change the stack, as otherwise could either not be synchronized or the 1-turn condition is violated. To be more precise, must be the first letter of as otherwise we get stuck in and . The letter resets the machines and to their initial state and can only be read when the stack is empty as otherwise the machine gets stuck. In order to reach final states, both machines and must increase and decrease the stack by reading some word , but as soon as we increased the stack once, we are not allowed to reset the machine anymore due to the 1-turn condition. Hence, letters can only be read while the stack has not been changed yet. Note that for all three stack models, the construction enforces that any 1-turn synchronizing word brings into a configuration where the stack is empty. ∎

When considering automata as language accepting devices, there is no good use of 0-turn PDAs, as they cannot exploit their stack. This becomes different if synchronization requires to end in the same configuration, which means that in particular the stack contents are identical.

The problem 0-Turn-Sync-DPDA-Same is undecidable. The proof is by a straight-forward adaption of the previously presented constructions by getting rid of the check phase; instead, check with the same stack condition that the two words of the PCP coincide. As we never pop the stack, a 0-turn DPDA will be sufficient in the construction.

The picture changes again for other 0-turn stack models, but remains intractable.

The problems 0-Turn-Sync-DCA-Empty, 0-Turn-Sync-DCA-Same and 0-Turn-Sync-DCA-Arb are PSPACE-hard.


We give a reduction from DFA-Sync-Into-Subset. Let be a DFA with . We construct from a DCA where all unions are disjoint. For , and , set . For the letter , we set for states , and for states , we set . For we set and . All transitions not yet defined act as the identity and leave the stack unchanged.

First, assume there exists a word that synchronizes  into  in the DFA . Then clearly synchronizes  in the arbitrary stack model. Now, assume there exists a word that synchronizes  in the arbitrary stack model. Then, must contain at least two occurrences of  to bring all states into the sink state . In order to reach the states in  need to pass through the state but by doing so, it is noted on the stack if an active state transitions from into and only the active states coming from  are allowed to pass on to . In the stack content cannot be changed and hence the prefix of  up to the first occurrence of the letter  must have already synchronized  into  in the DFA . Note that can only be synchronized by a word that leaves all stacks empty, hence the result follows for all three stack models. ∎

The problems 0-Turn-Sync-DPDA-Empty and 0-Turn-Sync-DPDA-Arb are PSPACE-hard.


The claim follows from Theorem 5 by inclusion of automata classes. ∎

. In the empty stack model, the 0-turn condition forbids us to write anything on the stack at all. Hence, consider a 0-turn DPDA with state set as a DFA , with one additional state which is entered whenever the DPDA wants to push or pop anything. For each , run the PSPACE-algorithm for the Sync-From-Into-Subset instance . For the arbitrary stack model, due to the 0-turn condition, for each run only the symbol on top of the stack must be ever stored. Consider a 0-turn DPDA with state set and stack alphabet as a DFA with state set and one additional state which is entered whenever the DPDA wants to pop anything. For each , run the PSPACE-algorithm for the Sync-From-Into-Subset instance .

1-Turn-Sync-DCA-Empty, 1-Turn-Sync-DCA-Same, and 1-Turn-Sync-DCA-Arb in PSPACE. Notice that PSPACE-hardness is inherited from corresponding results for visibly counter automata, as obtained in [vpda-crossref].


Let be a DCA. As we are looking into 1-turn behavior, any computation that we are interested would split into two phases: in the first upstroke phase, the counter is incremented or stays constant, while in the second downstroke phase, the counter is decremented or stays constant. In particular, because the counter is 1-turn, after the first counter increment, any zero-test will always return false, while in the downstroke phase, when zero-tests return true, then all future computations cannot decrement the counter any further, so that at the end, the counter will also contain zero. We are formalizing this intuition to create a machine that has an awareness about its phase stored in its states and that is behaving very similar. In the rest of the proof, a spread-out variant of a word of length , with symbols from , is any word in of length .

We will now construct from and a deterministic 1-turn counter automaton that accepts precisely all spread-out variants of words that would accept when starting in state and finishing its 1-turn computation (in any state) with the empty stack, but that keeps track of a basic property of managing the counter in so-called stages. has the state set , as its initial state, and as its set of final states, take . The transitions of can be defined with the following semantics in mind (details are given in the appendix): (a) the last bit always alternates, (b) the spread-out is used to enable a deterministic work and to make sure that the simulated machine has counter content zero if the simulating automaton  is in one of the states from , (c) changes from to if the counter is no longer zero, so that the simulated machine has “properly” entered the upstroke phase, (d) changes from to if the simulated machine made its first pop, i.e., it “properly” entered the downstroke phase, (e) changes from to if the counter has become zero again.

Now, we build the -fold product automaton from all automata with the start state , assuming . This means that has many states and many counters, each of which makes at most one turn. Now observe that a word synchronizes with empty stack, say, in state , if and only if any spread-out variant of drives into a state for some for all . Now, define as final states of . We see that is synchronizable with empty stack if and only if accepts any word. As Gurari and Ibarra have shown in [DBLP:journals/jcss/GurariI81, Lemma 2], accepts any word if and only if it accepts any word up to length ,111In the cited lemma, the number of steps of the checking machine is upper-bounded by , where is the number of 1-turn counters and is the number of transitions of the machine. within the same time bounds. Now, testing all these words for membership basically needs two counters that are able to capture numbers of size , which means we need polynomial space in and to check if is synchronizable with empty stack.

By considering with final states for arbitrary and , this way defining an automaton , we can check if is synchronizable in the arbitrary stack model also in polynomial space with the same argument. From , we can also construct a nondeterministic 1-turn -counter machine by adding a nondeterministic move from for arbitrary and upon reading some arbitrary but fixed to a special state in which state we loop upon reading , decrementing all counters at the same time; finally, there is the possibility to move to (that is the only finaly state now) upon reading if all counters are empty. Notice that also this automaton has many transitions, so that with using [DBLP:journals/jcss/GurariI81, Lemma 2], we can again conclude that synchronizability with same stack can be checked in polynomial space for . ∎

6 Sequential Transducers

We will now introduce a new concept of synchronization of sequential transducers.222The definitions in the literature are not very clear for finite automata with outputs. We follow here the name used by Berstel in [DBLP:books/lib/Berstel79]; Ginsburg [Ginsburg66] called Berstel’s sequential transducers generalized machines, but used the term sequential transducer for the nondeterministic counterpart. We call a sequential transducer (ST for short) if is a finite set of states, is a finite input alphabet, is a finite output alphabet, is the start state, is a total transition function, and is a set of final states. We generalize from input letters to words by concatenating the produced outputs, i.e., for , , and transitions we define . We say that a word trace-synchronizes a sequential transducer if for all states it holds that . Intuitively, brings all states of to the same state and produces the same output on all states. Again, we might neglect start and final states.

Given: Sequential transducer .
Question: Does there exists a word that trace-synchronizes ?
The problem Trace-Sync-Transducer is undecidable.


We adapt the construction of in Theorem 5 to obtain a sequential transducer in the following way: Each time, we push a letter to the stack in or , instead we now output this letter. Whenever we leave the stack unchanged, we now simply do not produce any output. For the letter , we output the special letter on all states in order to indicate that the machine has been reset. For the state we output the special letter and for the special letter , for all input symbols expect .

We make the following observations for any potential trace-synchronizing word for : (1) needs to start with . (2) needs to contain the sub-word . (3) The sub-word between the first occurrence of and the respective last occurrence of before describes a solution of the PCP instance. (4) If the PCP instance has a solution, one can construct a trace-synchronizing word for from that solution. ∎

7 Prospects

It would be interesting to look into the synchronization problem for further automata models. In view of the undecidability results that we obtained in this paper, a special focus should be to look into deterministic automata classes with a known decidable inclusion problem, as otherwise it should be possible to adapt our undecidability proofs for synchronizability to these automata models. To make this research direction more clear: (a) There are quite efficient algorithms for the inclusion problem for so-called very simple deterministic pushdown automata, see [WakTom93]; (b) a proper super-class of these languages are so-called NTS languages that also have a deterministic automaton characterization333This is rather implicit in the literature, which is one of the reasons why we do not present more details here; one would have to first define the automaton model properly. but their inclusion problem is undecidable, see [DBLP:journals/jcss/Senizergues85, DBLP:journals/jcss/BoassonS85]. The overall aim of this research would be to find the borderline between decidable and undecidable synchronizability and, moreover, within the decidable part, to determine the complexity of this problem. A step in this research direction has been made in direction of (sub-classes of) visibly deterministic pushdown automata in [vpda-crossref]. Interestingly enough, that research line also revealed some cases where synchronizability can be decided in polynomial time, quite in contrast to the situation found in the present study.

Another approach is to look into variants of synchronization problems for DPDAs, such as restricting the length of a potential synchronizing word. It follows from the NP-hardness of this problem for DFAs [Rys80, DBLP:journals/siamcomp/Eppstein90] and the polynomial-time solvability of the membership problem for DPDAs that for unary encoded length bounds this problem is NP-complete for DPDAs as well, and contained in EXPTIME for binary encoded length bounds. The precise complexity of this problem for binary encoded length bounds will be a topic of future research.


8 Appendix: Omitted Proof Details

Proof of Proposition 2.

The PSPACE-hardness can easily be inherited from the PSPACE-complete problem DFA-Sync-Into-Subset by setting and on a DFA-Sync-Into-Subset instance consisting of a DFA , and subset .

For membership in PSPACE, we adapt the proof in [San2005, Theorem 1.22] and give a non-deterministic algorithm for solving DFA-Sync-From-Into-Subset in NPSPACE. The claim then follows by Savitch’s famous theorem showing  [DBLP:journals/jcss/Savitch70]. Let , be an instance of DFA-Sync-From-Into-Subset. We start on the set and guess a symbol . Applying to all states in gives us the set . We continue in this way by guessing a symbol and applying it to the current set to obtain until we reach a set for which holds and the algorithm terminates with a positive answer. At each step, we only need to keep the current set in memory such that the algorithm can be performed in polynomial space. ∎

Proof of Theorem 5.

The following construction is an easy adaption of the previously presented constructions by getting rid of the check phase and instead check that the two words of the PCP coincide with the same stack condition. As we de not pop the stack a 0-turn DPDA will be sufficient in the construction.

Let , be an instance of PCP. We construct from  a real-time 0-turn partial DPDA where are marked numbers from 1 to . The set contains the states and . The rest of is a partition into states such that the (deterministic partial) sub-automaton induced by reads the string and thereby pushes each symbol of on the stack whereas symbols of leave the stack unchanged. The sub-automaton induced by is embedded into , by taking the state after reading to with the symbol . We go from and to the initial state of the sub-automaton induced by by the letter . If not stated otherwise, every transition leaves the stack content unchanged.

For the list , we construct a real-time 0-turn partial DPDA in a similar way, except that here we push the strings on the stack and symbols of strings leave the stack unchanged.

We combine the two machines and into a real-time 0-turn complete DPDA where all unions are assumed to be disjoint. The transition function agrees with and on all states in and letters in . For the letter we set for all states with , and for , . For and we set . For we set and for all other transitions we stay in and add a 1 on top of the stack. For we set and for all other transitions, we stay in and leave the stack unchanged. With all other not yet defined transition in , we go to and add a 1 on top of the stack.

Following previous arguments, it is clear that any synchronizing word for in the same stack model must start with the letter and contain at at least one sequence . Further, let with be the position of the first occurrence of a sequence and let with be the position of the last occurrence of before position . Then, the sub-word describes a solution for the PCP instance. Conversely, a solution of the PCP can be embedded in a synchronizing word for . ∎

The following proof gives proof details that do not completely follow the proof sketch of the main text, but are rather showing the power of the problem Sync-From-Into-Subset as a means for showing PSPACE-membership.

Proof of Theorem 5.

We prove the claims for DPDAs, as DCAs are a subclass hereof. Let be a DPDA. We first focus on 0-Turn-Sync-DPDA-Empty. As we need to synchronize with an empty stack, the 0-turn condition forbids us to write anything on the stack at all. Hence, we only keep in transitions of the form for , and delete all other transitions from . We call the obtained automaton . We may observe that is basically a partial DFA and the problem of synchronizing with a 0-turn synchronizing word in the empty stack model has been reduced to synchronizing without using an undefined transition. The latter problem is called the Careful Synchronization problem and is solvable in PSPACE [DBLP:journals/mst/Martyugin14]. Notice that the argument given in the proof sketch in the main text can also be seen as an alternative proof (or, it can be easily adapted to this end) of PSPACE-membership of Careful Synchronization.

For the problem 0-Turn-Sync-DPDA-Arb it is sufficient for each run to only keep the symbol on top of the stack in memory, as we are not allowed to decrease the height of the stack at any time, but transitions might still depend on the symbol on top of the stack. As we have no restriction on the stack content for synchronization, we can safely forget all other symbols on the stack. Hence, we can construct from a partial DFA with state set by re-interpreting transitions for as and deleting transitions of the form . The problem of synchronizing with a 0-turn synchronizing word in the arbitrary stack model has now been reduced to finding a word that brings all states of with into one of the sets for without using an undefined transition. We can solve this problem using polynomial space by guessing a path in the -fold product automaton . The automaton with state set , consisting of -tuples of states in , and alphabet , is defined based on by simulating the transition function of on every single state in a -tuple state of independently, yielding the transition function of . Here, is only defined on a -tuple if and only if is defined on every state of this tuple. Clearly, the size of is and we can guess a path from the state for to one of the sets for using space . We conclude the proof with Savitch’s famous theorem proving  [DBLP:journals/jcss/Savitch70]. ∎

Details of the construction of the transition function of in the proof of Theorem 5.

We now explain how to build the transition function of from the specification of .

  • Whenever there is a transition in , can transition from to upon reading , leaving its counter untouched. Formally, this means that in . Moreover, for any state and any letter , in . Notice that in this stage one, knows that the counter is zero. In particular, any word read in this stage could be accepted.

  • If there is a transition