Storage-Class Memory Hierarchies for Scale-Out Servers
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With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature of in-memory services makes seamless integration of SCM in servers questionable. In this paper, we ask the question of how best to introduce SCM for such servers to help improve overall performance per cost over existing DRAM-only architectures. We first show that even with the best latency projections for SCM, the higher memory access latency results in prohibitive performance degradation. However, we find that deploying a modestly sized high-bandwidth stacked DRAM cache makes SCM-based memory competitive. The high degree of spatial locality in-memory services exhibit not only simplifies the DRAM cache's design as page-based, but also enables the amortization of increased SCM access latencies and mitigation of SCM's read/write latency disparity. We finally perform a case study with PCM, and show that a 2 bits/cell technology hits the performance/cost sweet spot, reducing the memory subsystem cost by 40 performing DRAM-only system, whereas single-level and triple-level cell organizations are impractical for use as memory replacements.
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