Resistive Neural Hardware Accelerators

09/08/2021
by   Kamilya Smagulova, et al.
37

Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges associated with the growing amount of data and are exponentially increasing the complexity of computations. An emerging non-volatile memory (NVM) devices and processing-in-memory (PIM) paradigm is creating a new hardware architecture generation with increased computing and storage capabilities. In particular, the shift towards ReRAM-based in-memory computing has great potential in the implementation of area and power efficient inference and in training large-scale neural network architectures. These can accelerate the process of the IoT-enabled AI technologies entering our daily life. In this survey, we review the state-of-the-art ReRAM-based DNN many-core accelerators, and their superiority compared to CMOS counterparts was shown. The review covers different aspects of hardware and software realization of DNN accelerators, their present limitations, and future prospectives. In particular, comparison of the accelerators shows the need for the introduction of new performance metrics and benchmarking standards. In addition, the major concerns regarding the efficient design of accelerators include a lack of accuracy in simulation tools for software and hardware co-design.

READ FULL TEXT

page 8

page 18

page 25

page 27

page 29

page 30

page 32

page 33

research
03/16/2022

Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

Deep Neural Networks (DNNs) are very popular because of their high perfo...
research
01/28/2023

Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics

Domain-specific machine learning (ML) accelerators such as Google's TPU ...
research
08/24/2021

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators

Tiled spatial architectures have proved to be an effective solution to b...
research
06/10/2022

Real-time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators

In this paper we present Hyper-Dimensional Reconfigurable Analytics at t...
research
09/09/2021

3D Real-Time Supercomputer Monitoring

Supercomputers are complex systems producing vast quantities of performa...
research
12/23/2020

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators

The everlasting demand for higher computing power for deep neural networ...
research
06/12/2023

On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators

Deep Neural Networks (DNNs) have demonstrated impressive performance acr...

Please sign up or login with your details

Forgot password? Click here to reset