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Relay: A High-Level Compiler for Deep Learning
Frameworks for writing, compiling, and optimizing deep learning (DL) mod...
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Relay: A New IR for Machine Learning Frameworks
Machine learning powers diverse services in industry including search, t...
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RVSDG: An Intermediate Representation for Optimizing Compilers
Intermediate Representations (IRs) are central to optimizing compilers a...
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PointEval: On the Impact of Pointer Analysis Frameworks
Pointer analysis is a foundational analysis leveraged by various static ...
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LLHD: A Multi-level Intermediate Representation for Hardware Description Languages
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VH...
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The Collection Virtual Machine: An Abstraction for Multi-Frontend Multi-Backend Data Analysis
Getting the best performance from the ever-increasing number of hardware...
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Retrofitting Symbolic Holes to LLVM IR
Symbolic holes are one of the fundamental building blocks of solver-aide...
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Relay: A High-Level IR for Deep Learning
Frameworks for writing, compiling, and optimizing deep learning (DL) models have recently enabled progress in areas like computer vision and natural language processing. Extending these frameworks to accommodate the rapidly diversifying landscape of DL models and hardware platforms presents challenging tradeoffs between expressiveness, composability, and portability. We present Relay, a new intermediate representation (IR) and compiler framework for DL models. The functional, statically-typed Relay IR unifies and generalizes existing DL IRs and can express state-of-the-art models. Relay's expressive IR required careful design of the type system, automatic differentiation, and optimizations. Relay's extensible compiler can eliminate abstraction overhead and target new hardware platforms. The design insights from Relay can be applied to existing frameworks to develop IRs that support extension without compromising on expressivity, composibility, and portability. Our evaluation demonstrates that the Relay prototype can already provide competitive performance for a broad class of models running on CPUs, GPUs, and FPGAs.
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