Reconfigurable multiplier architecture based on memristor-cmos with higher flexibility
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Multiplication is an indispensable operation in most of digital signal processing systems. Recently, many systems need to execute different types of algorithms on a multiplier. Therefore, it needs complicated computation and large area occupation. In this regard a fixed multiplier is inefficient and the development of a reconfigurable multiplier becomes increasingly important. The advent of memristor-CMOS hybrid circuits provides an opportunity for reducing area occupation. This paper introduces memristor-CMOS based reconfigurable multiplier which provides flexible multiplication according to various bit-width. Performance of the proposed multiplier is estimated with some applications and comparison with conventional multipliers, using memristor SPICE model and proprietary 180-nm CMOS process.
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