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Worksharing Tasks: An Efficient Way to Exploit Irregular and Fine-Grained Loop Parallelism
Shared memory programming models usually provide worksharing and task co...
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Exploration of Fine-Grained Parallelism for Load Balancing Eager K-truss on GPU and CPU
In this work we present a performance exploration on Eager K-truss, a li...
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Accelerating Irregular Computations with Hardware Transactional Memory and Active Messages
We propose Atomic Active Messages (AAM), a mechanism that accelerates ir...
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Facilitating the Communication of Politeness through Fine-Grained Paraphrasing
Aided by technology, people are increasingly able to communicate across ...
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Network Pruning for Low-Rank Binary Indexing
Pruning is an efficient model compression technique to remove redundancy...
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Prediction of Compression Index of Fine-Grained Soils Using a Gene Expression Programming Model
In construction projects, estimation of the settlement of fine-grained s...
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Optimizing the Data Movement in Quantum Transport Simulations via Data-Centric Parallel Programming
Designing efficient cooling systems for integrated circuits (ICs) relies...
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Performance optimization and modeling of fine-grained irregular communication in UPC
The UPC programming language offers parallelism via logically partitioned shared memory, which typically spans physically disjoint memory sub-systems. One convenient feature of UPC is its ability to automatically execute between-thread data movement, such that the entire content of a shared data array appears to be freely accessible by all the threads. The programmer friendliness, however, can come at the cost of substantial performance penalties. This is especially true when indirectly indexing the elements of a shared array, for which the induced between-thread data communication can be irregular and have a fine-grained pattern. In this paper we study performance enhancement strategies specifically targeting such fine-grained irregular communication in UPC. Starting from explicit thread privatization, continuing with block-wise communication, and arriving at message condensing and consolidation, we obtained considerable performance improvement of UPC programs that originally require fine-grained irregular communication. Besides the performance enhancement strategies, the main contribution of the present paper is to propose performance models for the different scenarios, in form of quantifiable formulas that hinge on the actual volumes of various data movements plus a small number of easily obtainable hardware characteristic parameters. These performance models help to verify the enhancements obtained, while also providing insightful predictions of similar parallel implementations, not limited to UPC, that also involve between-thread or between-process irregular communication. As a further validation, we also apply our performance modeling methodology and hardware characteristic parameters to an existing UPC code for solving a 2D heat equation on a uniform mesh.
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