Performance Analysis of 6T and 9T SRAM
share
The SRAM cell is made up of latch, which ensures that the cell data is preserved as long as power is turned on and refresh operation is not required for the SRAM cell. SRAM is widely used for on-chip cache memory in microprocessors, game software, computers, workstations, portable handheld devices due to high data speed, low power consumption, low voltage supply, no-refresh needed. Therefore, to build a reliable cache/memory, the individual cell (SRAM) must be designed to have high Static Noise Margin (SNM). In sub-threshold region, conventional 6T-cell SRAM experiences poor read and write ability, and reduction in the SNM at various fluctuation of the threshold voltage, supply voltage down scaling, and technology scaling in nano-meter ranges (180nm, 90nm, 45nm, 22nm, 16nm and 10nm). Thus, noise margin becomes worse during read and write operations compared to hold operation which the internal feedback operates independent of the access transistors. Due to these limitations of the conventional 6T SRAM cell, we have proposed a 9T SRAM that will drastically minimize these limitations; the extra three transistors added to the 6T topology will improve the read, hold and write SNM. The design and simulation results were carried out using Cadence Virtuoso to evaluate the performance of 6T and 9T SRAM cells.
READ FULL TEXT
