Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems
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This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This thesis applies the best tradeoff between reducing the number of used transistors, utilizing energy efficient transistor arrangements such as transmission gates, and applying the dual supply voltages to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction of over 73 percent in terms of transistor count for the THA and over 88 percent in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve and Monte Carlo analysis for major process variations, TOX, CNT Diameter, CNT Count, and Channel length, were studied.
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