Multi-Number CVT-XOR Arithmetic Operations in any Base System and its Significant Properties

11/30/2015
by   Jayanta Kumar Das, et al.
0

Carry Value Transformation (CVT) is a model of discrete dynamical system which is one special case of Integral Value Transformations (IVTs). Earlier in [5] it has been proved that sum of two non-negative integers is equal to the sum of their CVT and XOR values in any base system. In the present study, this phenomenon is extended to perform CVT and XOR operations for many non-negative integers in any base system. To achieve that both the definition of CVT and XOR are modified over the set of multiple integers instead of two. Also some important properties of these operations have been studied. With the help of cellular automata the adder circuit designed in [14] on using CVT-XOR recurrence formula is used to design a parallel adder circuit for multiple numbers in binary number system.

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I Introduction

Integral Value Transformations (IVTs) is a class of continuous maps in a discrete space and was introduced in the year 2009. A p-adic, k-dimensional, Integral Value Transformation is denoted by and it is a mapping from . When k=1, is defined as

where is the decimal conversion from the p-adic number and is non-negative p-adic integer represented as and the Rule number denoted by is a local mapping defined from to . Here is the decimal equivalent of the p-adic string in the truth table representation of the local map. For example, when , and say and for the two different Rule numbers and shown in TABLE I, the are calculated as and

Variable Rule
0 2 1
1 1 2
2 0 1
TABLE I: Truth Table of two 1-variable ternary functions (base 3) functions and

Like One dimensional, two dimensional p-adic, Rule denoted by is defined as . Similarly, k-dimensional can be defined. (Sometimes the symbol is used instead of as base of the number system)

Carry Value Transformation (CVT) which was initially defined in the year 2008 , later developed and elaborated in became a special case of when , and along with a padded in the LSB position of the output binary string. Thus is a two dimensional, Rule , binary with a padded in it where as is simply a two dimensional Rule binary as shown in TABLE II.

Variable Rule
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
TABLE II: Truth Table of two 2-variable Boolean functions and

Carry Value Transformations were studied in to produce self-similar fractal whose dimension is same as the dimension of the Sierpinski triangle. Further they have shown that can also be used to produce many periodic and chaotic patterns. Also, analytical and algebraic properties of were studied in . Different fractals having dimension in between and were studied in . Two most important properties of and Modified Carry Value Transformation (MCVT) were studied in . Where It has been shown that sum of two non-negative integers are equal to their and values i.e. in any number system and the number of iterations leading to either or does not exceed the maximum of the lengths of the two addenda expressed as binary strings i.e. the convergence behaviours of and were discussed. Some similar kind of transformations such as Extreme Value Transformation (EVT) , Variable Boolean Operation (2-VBO) , Integral Value Transformations (IVTs) are also used to manipulate strings of bits and applicable in pattern formations , solving Round Rabin Tournament problem , Collatz-like functions and so forth. Previously used adder circuits are combinational in nature and their complexity depends on number of logic gates used and the associated gate delays. In line with this Cellular Automata Machines , were studied in for efficient hardware design of some basic arithmetic operations where their complexity centered on number of clock cycles required to finish the computation instead of the gate delays.

The organization of this paper is as follows: In section II some of the preliminary concepts on and operation of two numbers in binary domain is highlighted (also, thoroughly elaborated in ). In section III we have discussed the and operations of many numbers in any base system and studied some of its important properties. In section IV a parallel architecture for multi number addition in binary number system has been proposed. In Section V conclusion for this article along with some future research planning have been added.

Ii Carry Value Transformation

The carry or overflow bits are usually generated at the time of addition between two -bit strings. In the usual addition process, carry value is always a single bit and if generated then it is added column wise with other bits and not necessarily save for further use. But the carry value defined in are the usual carries generated bit wise and stored in their respective places as shown in TABLE III.

carry value = 0
a =
b =
=
TABLE III: Carry generated in the column counted from LSB is saved in column.

Thus to find out the carry value we perform the bit wise operation of the operands to get a string of sum-bits (ignoring the carry-in) and simultaneously the bit wise ANDing of the operands to get a string of carry-bits, the latter string is padded with a on the right to signify that there is no carry-in to the LSB. Thus the corresponding decimal value of the string of carry bits is always an even integer. Precise form of is a mapping defined as to where is the set of strings of length on . More specifically, if and then where is an bit strings, belonging to set of non-negative integers and can be computed bit wise by logical AND operation followed by a which denotes no carry is generated in the LSB at the time of addition procedure.

Illustration 1.

Suppose we want to find out the of two non-negative integers say 11 and 14. First of all, we have to find out the binary representation of these numbers . Both are 4-bits numbers. The carry value is calculated as shown in TABLE IV:

Carry : 1 0 1 0
a : 1 0 1 1
b : 1 1 0 1
XOR : 0 1 1 0
TABLE IV: Carry generated in column is saved in column for .

Conceptually, in the general addition process the carry or overflow bit from each stage (if any) goes to the next stage so that, in each stage after the first (i.e. the LSB position with no carry-in), actually a 3-bit addition is performed instead of a bit addition by means of the full adder. Instead of going for this traditional method, what we do is that we perform the bit wise operation of the operands (ignoring the carry-in of each stage from the previous stage) and simultaneously the bit wise ANDing of the operands to get a string of carry-bits, the latter string is padded with a on the right to signify that there is no carry-in to the LSB (the overflow bit of this ANDing being always is simply ignored). In our example, bit wise gives and bit wise ANDing followed by zero-padding gives . Thus and equivalently in decimal notation one can write . Figure 1 shows the circuit diagram of CAM used for performing addition of two 4-bit numbers . This CAM is based on a recurrence relation

(1)

which has been proved to be valid for any base system [5].

Fig. 1: Figure shows the CAM design for 4-bit addition circuit

This CAM is used to design an adder circuit for multiple numbers in binary number system and proposed in section IV.

Iii CVT and XOR Operations of Many Numbers In Any Base System

Definition: For any number system in base and of non-negative integers is defined as follows: (here integers represented as )

Note: In general, result may not be in base system but the decimal conversion of is same as the method from base to base 10.

Theorem 1.

The recurrence relation in equation (1) is also valid for many numbers in any base system.
That is

The proof of the above theorem can be similarly seen by extending the proof in [5].

Illustration 2.

Suppose in ternary number system (i.e. and operation of decimal numbers are as follows:

and

.
So we have observed that .

Iii-a Important Corollaries

Following two important Corollaries i.e. Corollary 1 and Corollary 2 are trivially obtained from the definitions of CVT and XOR operations for any base system and for arbitrary numbers.

Corollary 1. From XOR definition, and iff is a multiple of . So )=0 iff is multiples of .

Corollary 2. Similarly from CVT definition, and iff . So )=0 iff .

Iii-B Important Properties of Multi Numbers CVT and XOR Operations in Binary Number System

Iii-B1 CVT-Property

Property 1.

For base system, if all the numbers are same then

  1. if is even, is equal to addition of numbers i.e. times) times= .

  2. if

    is odd,

    is equal to addition of numbers i.e. times) times=.

Illustration 3.

For base and take X=5 (101)
if K is even (say K=4) then

if K is odd (say K=5) then
.

Property 2.

For base system, if and let is a scalar quantity and is a power of then

  1. and

  2. ; where

Illustration 4.

For base and let and .
then
and
.

Property 3.

If and
then

Illustration 5.

For base and let and .
and
then
.

Property 4.

If then .

Illustration 6.

For base and let , K=3 then
.

Iii-B2 XOR-Property

Property 5.

If all the numbers are same then

  1. if is even, of numbers is zero i.e. times) .

  2. if is odd, of numbers is equal to a single number i.e. times) .

Illustration 7.

For base and take X=5 (101)
if K is even (say K=4) then

if K is odd (say K=5) then
.

Property 6.

For base system, if and let is a scalar quantity and is a power of then

  1. and

  2. .

Illustration 8.

For base and let and .
then
and
.

Property 7.

If and then

Illustration 9.

For base and let and .
and
then
.

Property 8.

If then .

Illustration 10.

For base and let , K=2 then
.

Iv Proposed adder circuit for multiple numbers in binary number system

The Figure 2 shows the circuit design for -bit numbers using CAM. Where CAMs are required. For each CAM internal circuit design is throughly elaborated in and also shown in Figure 1. Initially in first level, computation is performed on 8 CAMs for two numbers pairwise in parallel. Output from each CAMs are forwarded to the second level CAMs and so on. Delay in each level is . So maximum delay is unit.

Fig. 2: Circuit design using CAMs for performing addition of sixteen 4-bit numbers in parallel

Acknowledgment

The authors would like to give anonymous thank to Dr. Sk Sarif Hassan for providing valuable suggestions to work with this domain.

V Conclusion

Here we have seen how to perform the Multi-Number and Operation in any base system. Some important properties of these operations are highlighted both in any base and binary number system. The implementations of this multi number arithmetic operations in binary system using parallel adder circuit has been proposed. In this context another parallel adder circuit design can be performed on using recurrence relation where lesser number of CAMs are required compare to the circuit design shown in Figure 2.

References