Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors

by   Markus Velten, et al.

Modern processors, in particular within the server segment, integrate more cores with each generation. This increases their complexity in general, and that of the memory hierarchy in particular. Software executed on such processors can suffer from performance degradation when data is distributed disadvantageously over the available resources. To optimize data placement and access patterns, an in-depth analysis of the processor design and its implications for performance is necessary. This paper describes and experimentally evaluates the memory hierarchy of AMD EPYC Rome and Intel Xeon Cascade Lake SP server processors in detail. Their distinct microarchitectures cause different performance patterns for memory latencies, in particular for remote cache accesses. Our findings illustrate the complex NUMA properties and how data placement and cache coherence states impact access latencies to local and remote locations. This paper also compares theoretical and effective bandwidths for accessing data at the different memory levels and main memory bandwidth saturation at reduced core counts. The presented insight is a foundation for modeling performance of the given microarchitectures, which enables practical performance engineering of complex applications. Moreover, security research on side-channel attacks can also leverage the presented findings.


page 2

page 3

page 6

page 7

page 9

page 10


Coherence Traffic in Manycore Processors with Opaque Distributed Directories

Manycore processors feature a high number of general-purpose cores desig...

Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors

Hardware platforms in high performance computing are constantly getting ...

Understanding Memory Access Patterns Using the BSC Performance Tools

The growing gap between processor and memory speeds results in complex m...

An analysis of core- and chip-level architectural features in four generations of Intel server processors

This paper presents a survey of architectural features among four genera...

Harvesting L2 Caches in Server Processors

We make three observations in modern processors: (1) LLC capacity is get...

R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors

AIoT processors fabricated with newer technology nodes suffer rising sof...

Modeling memory bandwidth patterns on NUMA machines with performance counters

Computers used for data analytics are often NUMA systems with multiple s...

Please sign up or login with your details

Forgot password? Click here to reset