Inverse design of photonic devices with strict foundry fabrication constraints

by   Martin F. Schubert, et al.
The Team at X

We introduce a new method for inverse design of nanophotonic devices which guarantees that designs satisfy strict length scale constraints – including minimum width and spacing constraints required by commercial semiconductor foundries. The method adopts several concepts from machine learning to transform the problem of topology optimization with strict length scale constraints to an unconstrained stochastic gradient optimization problem. Specifically, we introduce a conditional generator for feasible designs and adopt a straight-through estimator for backpropagation of gradients to a latent design. We demonstrate the performance and reliability of our method by designing several common integrated photonic components.


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I Introduction

Integrated photonic devices have led to game changing new capabilities in applications ranging from high-speed communications [1] to next-generation quantum computing platforms [2] and machine learning hardware accelerators [3]. These platforms stand to benefit from photonic components with improved performance, lower losses, larger bandwidths, and more compact footprints. However, achieving such multi-faceted specifications is extremely challenging through conventional intuition-backed design methodologies. In contrast, computational inverse design techniques can efficiently explore complex and high-dimensional design landscapes which are inaccessible to human designers. Enabled by adjoint variable methods [4, 5], gradient-based optimization techniques have proven to be among the most successful at producing photonic devices with high performance, with examples including wavelength-selective elements (e.g. multiplexers, filters, and resonators), signal routing elements (e.g. waveguide bends and couplers), and active components (e.g. modulators) [6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16].

The approach in gradient-based design strategies is to first formulate an objective function, calculated in terms of a device’s simulated performance. Adjoint methods allow these objective functions and their gradients to be efficiently computed at a cost of only two full-wave simulations [4, 5]

, independently of the number of degrees of freedom in a design. When used in the context of modern automatic differentiation frameworks (e.g. JAX and TensorFlow), these techniques enable powerful end-to-end device optimization frameworks

[14, 17]. However, guaranteeing that an optimized design yields the desired performance, while simultaneously satisfying the numerous design rules of modern semiconductor manufacturing processes [18], still poses a major challenge. Particularly relevant for integrated photonic devices are the capabilities of the lithographic systems, which define constraints such as the minimum feature length scale that can be reliably printed. Elements of a design which are smaller than this length scale may print inconsistently or may be completely absent in the fabricated structure. Moreover, inclusion of a design feature with sub-resolution size can have broad yield implications. Thus, semiconductor foundries specify design rules which define the minimum width and minimum spacing of design features. Compliance with these rules, as validated by a design rule check (DRC), is typically a prerequisite for fabrication.

There have been many proposals for DRC-compliant inverse design strategies. One class of strategies selects a design parameterization with intrinsic geometric length scale guarantees, e.g. by optimizing the placement of geometric primitives which already satisfy the desired minimum feature size constraints [19]. A related approach uses a parameterization which enables analytic constraints to be applied directly to the design degrees of freedom, e.g. by optimizing the coordinates of polygon vertices comprising shapes in the design mask [20]. However, the drawback in both of these strategies is that they offer up a limited landscape of potential designs. For example, when optimizing the vertices of a polygon, an optimizer will be unable to alter the topology of a design by closing or opening holes.

In contrast, topology optimization strategies open up a much larger design landscape by parameterizing a design as a pixelated image, which is transformed by a sequence of convolutional filters and pixel-wise nonlinear functions [21, 22, 23, 24, 16]. These so-called density or three-field parameterizations allow a gradient-based optimization algorithm (e.g. LBFGS or MMA [25]

) to modify any pixel within the design and apply arbitrary changes to the topology. In practice however, there is typically a trade-off between managing design feasibility (binarization of the pixels and feature size constraints) and attaining high performance because a continuous optimizer must traverse

infeasible regions of the design landscape before reaching feasible regions, which may or may not have high performance. The most common strategy in topology optimization is to begin with a continuous optimization phase before gradually enabling binarization and applying constraints. However, if binarization is ramped up too quickly, a continuous optimizer will stall and fail to make progress towards improving performance. Similarly, constraints or penalties on the feature size must be introduced in a way which will not push the optimizer away from high performance regions of the parameter space, where no guarantees remain on it being able to recover. Often, the detailed strategy and schedule for successfully enforcing feasibility is somewhat of an art and, moreover, depends on both the device being optimized as well as the performance objective, making it challenging to scale these strategies.

In this work we propose an always feasible gradient-based inverse design framework with strict guarantees on DRC compliance. The key features of our proposal are a conditional generator for feasible designs, which is combined with a straight-through estimator (STE) to enable gradient backpropagation. The combination of these two components yields a differentiable transform which can be incorporated into an computational graph, much like a convolutional filter or projection operator in density-based topology optimization. We apply our framework to several practical photonic design challenges (a waveguide bend, a beam splitter, a waveguide mode converter, and a demultiplexer), and demonstrate that the approach yields designs with high performance.

Ii Designs strictly satisfying length scale constraints

In this section, we introduce a mathematical framework for measuring whether a binarized pixel array is DRC-compliant, focusing on the minimum width and minimum spacing rules commonly required by semiconductor foundries. We consider binary arrays with values of and , and refer to these as void and solid, respectively. During the course of a fabrication workflow, such designs may be converted to contours by e.g. marching squares or dual contouring [26]. Conceptually, all such designs can be created by repeated placements and translations of void or solid brushes (i.e. kernels, or clusters of pixels), with the trivial single-pixel brush able to produce all designs. If a design is feasible with some brush , the condition


holds, where is the morphological opening of with brush ; this is computed by , where and are dilation and erosion operators [27]. Intuitively, morphological opening removes small features from an image, and if is unchanged by the operation then it only contains solid and void features that can be created with .

Length scale in a topology optimization context is typically associated with the minimum diameter of circular features. Thus, we say that if a design can be realized with an approximately circular brush with diameter , it has a minimum length scale of at least . The minimum length scale of the design is the largest value of for which Eqn. (1) is satisfied with brush . When contours are obtained by dual contouring (i.e. outlining pixels, for binary designs), a design with minimum length scale will also have related minimum width and spacing, equal to the minimum width of the brush itself. An example circular brush with associated measurements is shown in Fig. 1a and an example design which is feasible with the circular brush is shown in Fig. 2a.

We turn now to minimum width and spacing constraints, as might result from foundry design rules. Given a minimum width and spacing constraint [28, 29], there are many brushes for which the associated feasible designs satisfy the constraint. The smallest of these is the notched square, i.e. a square brush which is solid everywhere except at the corners, as shown in Fig. 1b. An example design is in Fig. 2b. When the constraint requires a physical minimum feature width and spacing of , designs feasible with the notched square brush of width will satisfy the constraint, where is the design pixel pitch. Thus, if we can require that our designs are feasible with a notched square brush of width , we are also guaranteed to satisfy width and spacing rules of size . In Sec. III we utilize this to develop an inverse design method which produces designs that are guaranteed to satisfy width and spacing rules.

Although reasoning about minimum width and spacing is straightforward for dual-contoured designs feasible with the notched-square brush, we have also extensively validated that such designs are design-rule compliant using industry standard design software: KLayout [28] and Siemens Calibre Physical Verification [29].

Figure 1: (a) Circular brush with diameter 13, and (b) notched square brush with width 13.
Figure 2: Random designs feasible for (a) diameter-13 circular brush, and (b) width-13 notched square brush.

Iii Inverse design subject to strict length scale constraints

In this section we describe our method of inverse design subject to strict length scale constraints. We have shown that designs which are feasible with a certain brush (

-feasible) will satisfy minimum length scale or width and spacing constraints. Properly, this can be considered a combinatorial optimization problem. However, our approach is to approximately solve this problem, by transforming it into an unconstrained stochastic gradient optimization problem. Critically, we use a conditional generator for feasible designs and a straight-through estimator (STE) for backpropagation; these two components are discussed subsequently.

iii.1 Generator for feasible designs

In general, a binary design can be produced by dilation of binary arrays and with , i.e.


The arrays and are termed the solid and void touches of . We consider the generation of -feasible arrays as a process in which or are updated with a single-element change at each step. In this context, we introduce several touch states and pixel states which may be associated with each location at any step in the process.

Specifically, defining these for the solid case: existing solid pixels are those which are assigned to solid by some touch in . Impossible solid touches are those which would assign an existing void pixel to solid. Valid solid touches are those which are not impossible and not already in . Possible solid pixels are those obtained by dilating all existing or valid touches with , i.e. they are those pixels which are or may be solid in a feasible array. Required solid pixels are those which are not existing and not possible for void. Resolving solid touches are those which are valid and would assign solid to a required-solid pixel. Finally, free touches are valid but only color existing pixels. These solid touches and pixels are computed by,


Corresponding void touches and pixels can be computed with similar expressions. Fig. 3 shows an example of pixels and touches computed from the expressions above. A full example is worked through in the Appendix.

A scheme that generates feasible arrays is outlined in algorithm 1. The algorithm begins with empty and and loops until all pixels are existing for either solid or void. At each step, the pixel and touch states are updated. If free touches exist, all are selected. If resolving touches exist, one of these is selected; otherwise, any of the valid touches are selected.

Figure 3: Design, pixels, and touches for an example traversal using the width-5 notched square brush.
procedure Generator()
     initialize empty and
     while design is incomplete do
         update pixel and touch states
         if free touches exist then
              select all free touches
         else if resolving touches exist then
              select a single resolving touch
              select a single valid touch               
Algorithm 1 Generator for -feasible designs

If touch selection is random, the algorithm simply yields a random feasible design. In practice, we greedily select the best touch as computed from a pixel reward array ; the reward of a solid touch is the sum of elements set by the touch, while the reward of a void touch is the negative sum. With this change, the algorithm becomes a conditional generator of feasible designs, where biases the feasible design generation. The designs in Fig. 2 have been created by running the algorithm on the same random reward array.

To gain some intuition for why this scheme always produces feasible designs, consider that the algorithm will select exclusively solid or exclusively void until reaching a state where all remaining pixels are possible for both solid and void. In this state, no touch can lead to an invalid status. Since the starting state is one where all pixels are possible for both solid and void, we can see that the algorithm will never produce an invalid status.

We emphasize that the full space of feasible designs of brush is accessible by Algorithm 1. This can be clearly seen, since e.g. if is provided, where is any feasible design, the output of the algorithm will simply be .

iii.2 Straight through estimator

Algorithm 1

is not differentiable, and so it cannot be directly used with backpropagation in a gradient-based optimization setting. As a workaround, we draw inspiration from the field of binary and quantized neural networks, noting that binary optimization can be viewed as topology optimization with a minimum length scale equal to a single pixel. Binary and quantized neural networks often make use of a STE in training, to backpropogate gradients through binary activation functions or to latent weights from which low-precision weights are obtained

[30]. Specifically, in this approach one substitutes the gradient of a non-differentiable function with that of an estimator, i.e.


A typical estimator for binarization (i.e. with the sign function) is identity, although it has been found that estimators which approximate their forward-pass counterpart can yield better results [31].

iii.3 Computational graph

The complete computational graph for the inverse design problem is depicted in Fig. 4. A latent design is passed through a transform followed by the conditional generator, which produces a feasible design. We pass the design to an electromagnetic simulation engine which computes scattering matrix elements; these are the inputs to an objective function, which computes a scalar loss value. Optionally, we symmetrize the transform output to favor symmetric feasible designs. All operations in this graph are differentiable, with the exception of the generator — for which we use the STE. Thus, we can compute an estimated gradient of the loss with respect to the latent design.

Figure 4: Computational graph of our inverse design scheme. Downward arrows indicate the forward computation, while upward arrows correspond to backpropagation. Gray boxes represent operations and text represents arrays or results.

For both the transform and the estimator, we have found that


is a good choice, where

is a scalar hyperparameter in the range 2-8. The convolutional transform aids in the optimization, as it ensures that the reward array

is smooth and has an associated length scale, determined by the brush size. The latent design is randomly initialized with a bias so that the first feasible design is fully solid, and it is updated iteratively using the Adam scheme [32], which is a common choice for stochastic optimization problems in machine learning. We use a learning rate of 0.01, and and

for the decay of the gradient and second moment exponential moving averages, respectively.

Notably, our method does not require scheduling of hyperparameters or changes in parameterization during the course of an optimization, and gives a feasible design at every optimization step. We expect that this simplicity could be advantageous from the perspective of a photonic designer tasked with creating a new component.

iii.4 Objective function

In a practical design application, one is generally concerned with creating a component that satisfies a performance specification. We define the specification by defining a cutoff value for the magnitude for each relevant scattering parameter . There is also an implicit additional bound on the allowed values, imposed by the physics of the problem. For example, magnitudes greater than one are impossible for passive components. The range of allowed values is

. In general, the specification may constrain the behavior for various ports and multiple frequencies, and so each of these may be vectors. Our scalar objective function has the form,


where is a vector of signs matching the size of , which are positive where the cutoff specifies the maximum value, and negative where it specifies the minimum value.

Iv Nanophotonic optimization problems

In this section we apply our proposed inverse design framework to several integrated photonic components operating in the O-band, demonstrating designs for a waveguide bend, a mode converter, a beamsplitter, and a wavelength demultiplexer. All components are optimized for their characteristics within two 10 nm wavelength bands centered at 1270 nm and 1290 nm. Performance targets for the components are specified in terms of their scattering parameters, and are summarized in Table 1. Simulations of the components are performed using Ceviche [17]

, an open source 2D finite difference frequency domain (FDFD) simulator. Silicon (

) and silicon oxide () are used for solid and void materials, respectively. All components are coupled to waveguides having 400 nm width, and we deal with the fundamental waveguide mode unless noted otherwise.

-20 dB -20 dB -20 dB. -20 dB
-20 dB -20 dB -20 dB -20 dB
-0.5 dB -0.5 dB -3.5 dB -3 dB
-0.5 dB -0.5 dB -3.5 dB -20 dB
-3.5 dB -20 dB
-3.5 dB -3 dB
-20 dB
-20 dB
Table 1: Cutoff values for squared magnitude of scattering parameters for the 1270 nm and 1290 nm wavelength bands.

The waveguide bend features a design region, with waveguides connecting to the left (port 1) and bottom (port 2). Given excitation from port 1, we aim to maximize transmission to port 2 while keeping backreflection low. Diagonal reflection symmetry is imposed, so that excitation from port 2 yields identical behavior.

The spatial mode converter features a design region, with waveguides connecting to the left and right. We seek designs that maximally convert the fundamental waveguide mode on the left (port 1) to the second order mode on the right (port 2), with minimal backreflection into port 1.

The beamsplitter design region is in size, with two waveguides connecting to the left (port 1 and port 4) and two waveguides connecting to the right (port 2 and port 3). Given excitation from port 1, the beamsplitter aims to divide power equally into port 2 and port 3 while minimizing backreflection into port 1 or transmission into port 4. We impose reflection symmetry along the horizontal and vertical axes, so that excitation from any other port yields identical behavior.

The wavelength demultiplexer features a design region, with one waveguide connecting to the left (port 1) and two waveguides connecting to the right (port 2 and port 3). Given excitation from port 1, wavelengths in the first band are directed to port 2 while wavelengths in the second band are directed to port 3.

In the optimization context, we consider three wavelengths per band — the center and extremal wavelengths. The specifications are considered to be fulfilled if the criteria in 1 are satisfied for all wavelengths. Our design resolution matches the 10 nm simulation resolution, so that e.g. a circular brush with diameter 10 corresponds to a 100 nm length scale.

V Results

Figure 5: Evolution of a waveguide bend with 100 nm circular brush. Left: field magnitude for 1280 nm excitation with overlaid design. Right: power transmission into port 1 and 2, given excitation from port 1.

v.1 Designs using 100 nm circular brush

Fig. 5 shows optimization results for the waveguide bend with 100 nm circular brush. Upon initialization, the design is entirely silicon with no enclosed oxide. The initial design is poor, with low transmission to the output port and substantial reflection back to the input port. Subsequent updates significantly modify the topology of the design, adding enclosed oxide features and developing isolated silicon features. We emphasize the key characteristic of our scheme — the design at every step is fully binary and satisfies the 100 nm length scale constraint.

The target performance specification is achieved in 28 optimization steps, and the design continues to improve with more iterations. The lowest loss in the first 160 steps is found at step 122. Notably, the topology of this design differs from that at step 28, due to the fusing of two void features and the elimination of a third, along with changes in the shape of some solid features. The ability of our scheme to change topology while remaining feasible stands in contrast to some other methods, where the optimizer is locked in to a fixed topology once the optimization reaches an advanced state.

Figure 6: Lowest loss designs achieved in the first 160 steps and their respective field magnitudes for (a) mode converter and (b) beamsplitter, both with 1280 nm excitation. Design and fields for the wavelength demultiplexer, with (c) 1270 nm and (d) 1290 nm excitation. All use a 100 nm circular brush.
Figure 7: Scattering spectra for the (a) mode converter, (b) beamsplitter, and (c) wavelength demultiplexer with 100 nm circular brush.

For the mode converter, beamsplitter, and wavelength demultiplexer, the lowest-loss design from the first 160 optimization steps and corresponding field magnitudes are shown in Fig. 6. The scattering spectra for each is shown in Fig. 7, where each satisfies the performance target laid out in Table 1 and the 100 nm length scale constraint.

As we have shown, the topology of a design can change substantially during the course of the optimization. Since the response of a device is generally discontinuous with major changes in the design shape or topology, a noisy loss trajectory is expected. This is illustrated in Fig. 8, which shows the normalized loss value versus iteration for the waveguide bend of Fig. 5 and the other three components. Points where the performance target is achieved are also highlighted. For each component, the loss generally decreases with step, but noise in the loss value and occasional regressions to higher loss can be seen.

The waveguide bend and mode converter require fewer than 40 optimization iterations to achieve the target. Meanwhile, the beamsplitter and demultiplexer appear to be relatively more difficult problems, requiring approximately 100 steps to first reach the target. However, this is still well within the range of optimization steps required in an inverse design scheme [16]. In general, difficulty is directly related to the target specifications, length scale constraints, the physical size of the component, and the configuration of connecting waveguides. Reducing the length scale or increasing the design size will expand the solution space, and generally allow satisfactory solutions to be found with fewer optimization steps.

Figure 8: Normalized loss trajectories with 100 nm circular brush. Markers indicate steps where the performance target from Table 1 is achieved.

v.2 Designs using 100 nm notched square brush

Figure 9: Normalized loss trajectories with 100 nm notched square brush. Markers indicate steps where the performance target from Table 1 is achieved.

Next, we turn to component designs generated using a 100 nm notched square brush. With the design resolution of 10 nm, these designs strictly satisfy an 80 nm minimum width and spacing constraint. The normalized loss trajectories four the components are plotted in Fig. 9. Scattering spectra and designs are found in the appendix.

For all components, designs achieving the performance target from Table 1 are found. However, the loss trajectories differ in several respects. Specifically, the trajectories are noisier, they generally contain fewer points that achieve the spec, and the spec is achieved later in the optimization. We attribute this to the fact that the notched square is relatively larger in area, limiting the design space accessible to the optimizer and making the problem more challenging. We expect that optimal hyperparameters of the Adam algorithm used to drive our optimization are somewhat problem-dependent, and in future work it would be interesting to explore various configurations. In particular, reducing the learning rate as the optimization progresses, which has been shown to aid in training of quantized neural networks [33], could be beneficial.

v.3 Reliability and effect of length scale

Our results indicate that our inverse design framework is capable of finding designs with desired performance for a variety of fabrication-constrained photonic inverse design problems. A useful method will find such solutions for a range of length scale constraints, and do so reliably. To evaluate this, we consider the optimization problems above for circular and notched-square brushes with 60 nm, 80 nm, 100 nm, and 130 nm size. To study reliability of the method, we run 20 separate 500-step optimizations with different random initialization, generating 320,000 feasible designs in the process.

Figure 10: Fraction of independent randomly-initialized optimization runs achieving the Table 1 target performance as a function of the optimization step, for each component. Left column: with circular brush. Right column: with notched square brush.

Our analysis proceeds as follows: for each step of an optimization run, we identify whether the target performance from table 1 is achieved at any step . Then, for each combination of component, brush shape, and brush size, we compute for each step the fraction of the 20 runs which achieve this target. The results are shown in Fig. 10.

Turning first to the 60 nm brushes: we observe that for all components and both brush shapes, we are able to consistently find solutions which achieve the performance target. Random initialization affects the optimization trajectory, and the 20 different runs produce a distribution in the number of steps required to achieve the target. Comparing the circular and notched square brush, we find that with the circular brush the target performance is achieved slightly earlier, consistent with the hypothesis that the notched square presents a more challenging optimization problem. This finding will be repeated for other brush sizes discussed below. Across all component types, the range of steps required to achieve the target performance is at most tens of steps wide, and in practical application a single optimization run may actually be sufficient to find a good solution.

With the 80 nm brushes, again we are able to consistently achieve the target performance. In general, the number of steps required is larger than for the 60 nm brush. However, in some cases — such as the wavelength demultiplexer with circular brush — the steps required follow similar distribution as with the 60 nm brush. This suggests that for some problems, decreasing the length below a threshold value has no benefit. We also see some outlier examples where the target fails to be achieved.

As the brush sizes are increased to 100 nm, the general pattern is repeated. The target performance is achieved with good consistency, but more steps are required and a larger number of outlier optimization runs fail to reach the target within 500 steps.

At 130 nm, the pattern is repeated yet again. With this brush size, designs for the waveguide bend and mode converter which achieve the target continue to be consistently found. For the beamsplitter and wavelength demultiplexer, however, approximately half or fewer optimization runs achieve the target. Therefore, in a practical application of our inverse design method with such large length scales, it may be beneficial to launch multiple optimization runs to ensure that at least one can reach the target performance.

Much of the data supports the conclusion that larger brushes present more challenging optimization problems. We expect this also for theoretical reasons, since the design space with small brushes is strictly larger than that for small brushes. However, with 130 nm brush we observe that some of the beamsplitter designs achieve the target performance ahead of the best 80 nm and 100 nm brush runs. This warrants further investigation in future work.

Vi Conclusion

We have described a novel inverse design method which produces designs that are guaranteed to satisfy length scale constraints throughout the course of an optimization. Our method uses a conditional generator for feasible designs, and adopts the straight-through estimator commonly used for quantized neural network training. This enables us to pose the problem of length-scale-constrained topology optimization as a simple unconstrained stochastic gradient optimization problem.

Our method is shown to reliably find good solutions to a variety of 2D nanophotonic inverse design problems. We believe the good performance of the method and its simplicity could make it a useful new scheme in practical applications of inverse design.

In the future, it would be important to use a realistic 3D electromagnetics simulator to design components that can be manufactured in commercial foundries. It would also be interesting to apply the method to topology optimization problems in other domains.

We also see possible improvements to the underlying method. Specifically, conditional generators for designs satisfying additional constraints would be valuable — such as minimum solid and void area, which are frequently included in foundry design rules. Even for width and spacing constraints addressed by the current scheme, it would be useful to develop new generators which are not conservative, i.e. which do not require a brush larger than the target minimum width. Finally, the estimator and transform functions warrant additional study, and we see potential for learned estimators.


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A1 Example feasible design generation

Figs. A1 and A2 illustrate the generation of a 68 feasible design in 12 steps, using Algorithm 1 and a notched-square brush having width 5.

Figure A1: The first six steps of design generation. Step 1: Solid and void touches are valid at all locations, and all pixels are possible. Step 2: A void touch is placed at A6. Pixels covered by the touch become existing pixels for void, and impossible pixels for solid. A7 becomes a free touch for void. Step 3: The free touch A7 is taken. The design and pixels are unaffected. Step 4: A solid touch is placed at A0. Step 5: A void touch is placed at E6. Location C4 becomes a required pixel for void. There are required-resolving touches in columns 3, 4, and 5, while there are free touches in columns 6 and 7. The resolving (but not free) touches would set C4 to void, but would also remove possible solid pixels. Step 6: All the free touches are taken. The required pixel C4 is resolved, and no required-resolving touches remain.
Figure A2: Additional steps of design generation. Step 7: A void touch is placed at D4. Pixels E0, E1, F0, and F1 are now required for void. Both free and resolving (but not free) void touches exist. Step 8: All the free touches are taken. E1 and F1 are resolved, but E0 and F0 remain required void pixels. Step 9: A void touch is placed at F0, and the required pixels are resolved. F1 and F2 are now free void touches. Step 10: The free touches at F1 and F2 are taken. Step 11: A void touch is placed at C5. Pixels at A3 and C2 are now required for void. Since all remaining pixels must now be void, only free void touches remain. Step 12: The free touches are made, and the design is complete.

A2 Designs using 100 nm notched square brush

Scattering spectra for components created with a 100 nm notched square brush are shown in Fig. A3. The corresponding designs are shown in Fig. A4. Each component is the lowest-loss component found in the first 160 optimization steps of a randomly-initialized optimization run.

Figure A3: Scattering spectra for the (a) waveguide bend, (b) mode converter, (c) beamsplitter, and (d) wavelength demultiplexer with 100 nm notched square brush.
Figure A4: Lowest-loss designs achieved in the first 160 steps and their respective field magnitudes for (a) the waveguide bend, (b) mode converter, and (c) beamsplitter with 1280 nm excitation. Design and fields for the wavelength demultiplexer, with (d) 1270 nm and (e) 1290 nm excitation. All use a 100 nm notched square brush.