Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures

06/10/2019
by   Shouvik Musavvir, et al.
0

Monolithic 3D (M3D) technology enables high density integration, performance, and energy-efficiency by sequentially stacking tiers on top of each other. M3D-based network-on-chip (NoC) architectures can exploit these benefits by adopting tier partitioning for intra-router stages. However, conventional fabrication methods are infeasible for M3D-enabled designs due to temperature related issues. This has necessitated lower temperature and temperature-resilient techniques for M3D fabrication, leading to inferior performance of transistors in the top tier and interconnects in the bottom tier. The resulting inter-tier process variation leads to performance degradation of M3D-enabled NoCs. In this work, we demonstrate that without considering inter-tier process variation, an M3D-enabled NoC architecture overestimates the energy-delay-product (EDP) on average by 50.8 SPLASH-2 and PARSEC benchmarks. As a countermeasure, we adopt a process variation aware design approach. The proposed design and optimization method distribute the intra-router stages and inter-router links among the tiers to mitigate the adverse effects of process variation. Experimental results show that the NoC architecture under consideration improves the EDP by 27.4 average across all benchmarks compared to the process-oblivious design.

READ FULL TEXT
POST COMMENT

Comments

There are no comments yet.

Authors

page 3

page 6

page 7

page 8

page 9

06/26/2018

Design of TDC ASIC based on Temperature Compensation

.On the basis of requirement of CSNS, we designed a TDC chip with temper...
07/07/2021

A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization

This article presents a reconfigurable physically unclonable function (P...
10/19/2021

PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory

Binary neural networks (BNNs) that use 1-bit weights and activations hav...
04/17/2019

Experimental Clock Calibration on a Crystal-Free Mote-on-a-Chip

The elimination of the off-chip frequency reference, typically a crystal...
07/31/2020

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

3D integration technologies are seeing widespread adoption in the semico...
11/30/2020

HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration

Heterogeneous manycore architectures are the key to efficiently execute ...
06/17/2021

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

With 3D-stacked DRAM architectures becoming more prevalent, it has becom...
This week in AI

Get the week's most popular data science and artificial intelligence research sent straight to your inbox every Saturday.