1 Introduction
In the competitive environment of semiconductor manufacturing, accurate reliability prediction results in significant timetomarket and profitability improvements. Prediction quality depends on the manufacturer’s ability to characterize processrelated instabilities and defects in a given design. Burnin stresses are commonly performed on products to accelerate the fabrication process failure mechanism and to screen out design flaws.
At submicron process technology nodes, it has been suggested that burnin stress is likely to affect the Negative Bias Temperature Instability (NBTI) [1], which in turn will affect the operational performance of circuits.
The objective of the work described in this paper is to evaluate the effect of burnin stress on NBTI, with reference to the performance effect on analogue circuits. A DigitaltoAnalogue Converter (DAC) module was selected as a case study. With device reliability models and circuit simulation, this paper analyses the effect of burnin stress on the shift of key DAC parameters such as the Integral NonLinearity (INL), Differential NonLinearity (DNL) and gain error.
2 Background
2.1 Nbti
Since the advent of 90nm CMOS technology, NBTI has become one of the top circuit reliability issues for both PMOS and NMOS devices, because it can severely impact product performance over time. Compared with previous process generations, NMOS hot electron degradation is no longer of such concern. At 45nm, Positive Bias Temperature Instability (PBTI) has an effect on NMOS devices that is about half of that of NBTI on PMOS devices [2].
Several studies have reported on the impact of NBTI on the performance of analogue and digital components. It was shown by Kang et al [3] that the degradation in maximum circuit delay closely follows the trend of thresholdvoltage () degradation in a single PMOS transistor. Their finding was based on a detailed analysis of circuit performance with respect to NBTI degradation, particularly focusing on the maximum delay degradation of randomlogic circuits. Kumar et al [4] confirmed the effect of NBTI degradation under AC conditions. In addition, Kufluoglu et al [5] addressed both PMOSlevel measurement delay effects and realtime degradation and recovery by simulation. A study performed by Bhardwaj et al [6] revealed that circuitlevel NBTI models can be further improved by considering various process technologydependent parameters which lead to process variation effects.
Ball et al [7] have explored the burnin implications for SRAM circuits. Their approach has demonstrated that the minimum operating voltage, , increases during burnin as a result of NBTI and is of the order of the NBTIinduced shift.
2.2 Simulation Model
Schroder and Babcock [1] have thoroughly studied the Time To Failure () relationship to voltage and temperature effects. From their analysis, is affected as follows:

when the burnin stress voltage, increases, decreases;

when the difference between the nominal voltage, , and increases, decreases; and

is inversely proportional to Temperature.
The worst case situation is when the system is operated at a high voltage most of the time. However, NBTI degradation can also affect the minimum operating voltage, , as noted above.
NBTI degradation is less sensitive to than is NMOS Hot Carrier (NHC) degradation. However, it is more sensitive to temperature [8] and occurs even when the transistor is not switching, as long as it is in inversion.
The following equation shows how the threshold voltage shift of a PMOS transistor, as a function of the applied voltage and temperature, affects the [9].
(1) 
(2) 
(3) 
(4) 
where

is the scaled time to failure in seconds due to voltage and temperature scaling dependencies;

is the mean time to failure at the selected fail criterion (FC);

is the geometry scaling function for ageing;

is the electric field acceleration factor;

is the electric field () across the gate oxide, of thickness ;

is the junction temperature;

is the thermal activation energy;

is the shift, defined as the failure criterion for modelling;

is a processdependent variable.
This effect can be simulated by applying a signal to the circuit of interest and summing the degradation from each time step. In this case, the effect of the shift in , the threshold voltage, for a time varying waveform, can be calculated by using the quasistatic time integral with time in equation (5).
(5) 
Lee et al demonstrated the NBTI effect on product reliability degradation [10]. In addition, their simulator includes other reliability mechanisms such as hot carrier injection (HCI) and timedomaindielectricbreakdown (TDDB) [10]. The simulation demonstrates the validity of using a TDDB degradation model to predict the failure rate of a complicated microprocessor. The model is derived using large discrete capacitor/device TDDB data with various temperature, voltage and geometry considerations.
It is noted that even though NBTI degradation occurs under elevated voltage and temperature, the NBTI phenomena show some relaxation. This occurs due to passivation of NBTIinduced silicon dangling bonds by the hydrogen which has diffused from the gate oxide to the interface [5]. There are two types of relaxation that need to be seriously considered for circuit reliability modelling.

Fast relaxation: This relaxation occurs as soon as the stress is removed. It is responsible for reduced AC degradation even after accounting for the transistor ‘ON’ time. However, this relaxation mode is not covered in our reliability simulations.

Extended relaxation: This relaxation occurs as the device is kept unbiased. Our reliability analysis accounts for this relaxation mode.
Figure 1 illustrates the two relaxation modes. Because relaxation lessens the effects of NBTI, a device under continuous usage may suffer a higher degradation than the reliability simulation predicts.
2.3 Assumptions of the reliability simulation model
We approximate a complex integrated circuit with a series failure model. We also assume each failure mechanism has an exponential lifetime distribution. In this way, the failure rate of each failure mechanism is treated as a constant. With these two assumptions, the reliability simulation models, which are often used to extrapolate failure rates, can be validated based on available data.
3 Reliability Simulation
For this work, Intel’s internal tool, RELSIM (Reliability Simulation), is used to predict changes in device and circuit performance over a product’s lifetime. It further allows simulation of postdegraded circuits to ensure circuit designs meet reliability requirements at endoflife (EOL) [11]. The reliability simulation methodology used in this paper is shown in Figure 2. The simulation has two modes of operation. The first mode, the Stress Mode, calculates the transistor shift. The second mode, the Playback Mode, simulates degraded circuit performance based on Stress Mode results. The simulation is conducted to cover elevated ranges of Process, Voltage and Temperature (PVT).
The DAC reliability simulation is run in a 3step process in the design environment.

Simulate the nondegraded behaviour at the typical circuit operating condition ( and temperature).

In Stress Mode, calculate the amount of degradation on each transistor. This is done at a slightly higher voltage and temperature to get a more conservative estimate of the degradation.

In Playback Mode, simulate the degraded circuit, using the degradation calculated in the Stress Mode.
The Stress Mode is used to report the degradation of a circuit at future times chosen by the user. The user provides the ageing time, the ageing method (e.g. none, fixed, uniform, bias and temperature user parameters) and a reference degradation value. Also necessary is a degradation parameter file that contains parameters for MOS device stress calculations. During the stress simulation, a stress file is generated at each specified future time. The stress file contains the stressed (degraded) values of each MOS device in the circuit. The degraded circuit values from the initial stress mode can be subsequently used in playback mode. The playback mode produces output signal waveforms for an aged circuit. The information from a stress file is read and a perturbation function is applied to the MOS depending on the degradation model chosen in the stress mode.
The reliability simulator has been used for transistor ageing modelling across major process technologies from 250nm down to 14nm [12]. The models have been extensively calibrated against actual silicon test chip data to ensure accuracy [12]. The simulator can be used to model the minimum () degradation effects. It is able to find the worst case corners, and takes voltages on all nodes into account. The AC NBTI modelling capability provides more accurate reliability performance predictions than static DC worstcase models. Furthermore, it can be calibrated with the AC circuits to include NBTI recovery, similar to that in [5].
Another key advantage of this reliability simulator is that the PMOS degradation is modelled with threshold voltage shifts based on nonuniform IV degradation. The simulator models the effect on the MOS transistors IV characteristics and the effect on the device parameters and applied voltages. Under the PMOS degradation model, it is suitable for both digital and analogue simulations.
4 Case Study : Digital Analogue Converter
For this case study a video DAC has been used. The performance of the DAC is critical for achieving excellent video quality. The required accuracy of the DAC is based on the differential gain and phase distortion specifications for TV [13]. The DAC is designed as a current steering architecture to achieve high accuracy and low distortion of the analogue video signal. The signal range is between zero volts to the maximum nominal analogue video signal swing of 1.3V. The digital input to each DAC is latched on the rising edge of each clock and is converted to an analogue current. For a given digital input, the current source outputs are summed together and directed to the output pin by the differential current switches. An analogue video voltage is created from the DAC output current flowing into the termination resistors. To determine the required output current of the DAC circuit, the video level specifications for the various video formats along with the effective load termination are measured. The LSB output voltage, which ranges between 684 V and 1.27 mV, is a function of the supported video format. Given the circuit mismatch sensitivity of this circuit, paired devices are designed accordingly; typically with greater lengths.
The DAC is composed of parallel current switches. This socalled CRT DAC is widely used in high speed applications specifically for its speed and linearity. The circuit is referenced to an analogue power supply which consists of an array of PMOS current sources and differential current switches (Figure 3).
This DAC operates at 3.3V nominal voltage and implemented in 90nm process technology. It has been shown that the 90nm CRT DAC has sufficient headroom in terms of the circuit performance degradation throughout a 7year lifetime.
The degradation is calculated by scaling the gate voltages to the typical analogue operating voltages. The extrapolation is given by equation (6) [9].
(6) 
where:

is the process related prefactor;

is the threshold voltage;

is the activation energy in eV ( = 0.145 eV was chosen by experiment)

is the transconductance parameter ( = 0.75 was chosen by experiment);

is the gate to source voltage;

is the Boltzmann Constant;

is the temperature in Kelvin;

is the time in years; and

is the voltage acceleration and exponent factor ( = 0.181 was chosen by experiment).
5 DAC ageing simulation and results
For our case study, NBTI analysis was performed on the DAC circuit shown in Figure 4. We simulated the NBTI behaviour of the DAC under normal and extreme conditions.
The reliability simulation playback mode analysis was done under the typical corners, for prelayout schematics with proper loading. For this analysis, the circuit was aged for a 7year lifetime to check the DAC circuit functionality and the effect of NBTI degradation under burnin conditions. Table 1 shows a comparison between three different conditions.
Parameters  Fresh  Burn In (Stressing Mode)  Age (Playback Mode) 

Stress Skew 
Typical Corner  Typical Corner  Typical Corner 
Stress Voltage  3.3V  4.6V  3.3V 
Temperature  100C  110C  110C 
Use time  Time 0  168 hrs  7 years 
We analysed the matched devices in Figure 4 and observed slightly different degradation behaviours. There are two key device parameters that are critical to degradation behaviours.

Drain current, : The current reaches its maximum value and maintains that value for higher draintosource voltages. A depletion layer located at the drain end of the gate accommodates the additional draintosource voltage. This behaviour is referred to as drain current saturation, . Drain current saturation therefore occurs when the draintosource voltage equals the gatetosource voltage minus the threshold voltage.

Threshold voltage, : A group of transistors has a Gaussian profile about a mean. Experimentally, it has been shown that the difference in threshold voltages between 2 identically sized transistors behaves as described in equation 7 [1].
(7) where is a technology conversion constant (in mVm), and WL denotes the product of the transistor’s active area.
From the simulation results, it is observed that the and the degradations of both the matched devices M1 and M2 pairs and the differential switch M3 and M4 pairs at 3.3V nominal condition of VCCA were comparable. The degradation at 3.3V for all transistors seems greater than that of the 4.6V burnin. However, the delta of 3.3V and 4.6V is not enough to conclude that degradation happens even at 3.3V nominal. On the other hand, the degradation shows a significant difference at the two voltage readings. At the 4.6V burnin condition, the degradation of the matched devices in both M1 and M2 pairs gives a mismatch of 5.2 mV, compared with the DAC specification of 2 mV, as shown in Table 2. These two current source pairs have a higher mismatch compared to the differential pairs. This mismatch may cause the DAC to malfunction.
For simulation purposes, the DAC performance data in Table 3 was simulated at 3.3V nominal as well as at 4.6V at elevated voltage. The performance data focused on the critical parameters:

Differential NonLinearity (DNL)

Integral NonLinearity (INL)

Gain Error

Offset Error

Output Current
From the simulation results, the DAC key performance parameters were generally within the specification criteria, by percentage change. However, it is noted that the gain error measurement of 2.68V at 4.6V is equivalent to a 7.2% change, slightly higher than the +/5% specification limit.
DAC Parameters  Spec  Sim#1 @ 3.3V  Sim#2 @ 4.6V  Percent Change 

DNL (20MHz)  +/1 LSB  0.1734 LSB  0.1803 LSB  3.98% 
INL (20MHz)  +/1 LSB  0.0387 LSB  0.0417 LSB  7.75% 
Gain Error  +/5%  2.500 V  2.68 V  7.20% 
Offset Error  +/5%  0.000387 V  0.000403 V  4.13% 
Output Current  021 mA  4.58 mA  4.93 mA  7.64% 
6 DAC burnin experiment
For the burnin experiment, the voltage supply of interest, the analogue CRT DAC power supply, VCCA, was elevated to a burnin voltage of 4.6V. The nominal voltage for this power supply is 3.3V. Three hundred units from three fabrication lots were analysed.
These units were subjected to burnin stress for 30 minutes followed by post burnin checkpoint (PBIC). All units completed a cumulative 168hour burnin. Of 300 experimental units, 30 good units were sampled for specific DAC burnin characterization. From these 30 samples, 1 unit from each of the three fabrication lots was marked as the control unit. These control units were tested first and used for reference, while the rest of the units were tested after each of the burnin phases at a temperature of 115C.
ATE testers were used to take a series of electrical measurements (timing and parametric shift) at different phases: preburnin, time zero, and followon (0.5 hours, 12 hours, and 168 hours burnin). The same five critical performance parameters as in the simulation were measured. Two sets of data were collected: at the nominal voltage of 3.3V; and at the elevated burnin voltage of 4.6V.
7 DAC burnin results and discussion
We present in Figure 5 experimental data from stressing discrete transistors that illustrates the increase in with respect to the NBTI stress time. The graph was plotted by applying the power law in equation (8).
(8) 
Figure 5 compares the results from time zero at 3.3V with those at 4.6V elevated voltage with respect to the stress time. It is apparent that NBTI has a powerlaw time dependence. When plotted on a loglog scale, we see that a higher voltage difference between gate and source will result in a higher degradation. This shows that has a powerlaw dependence with respect to time. As a result, the curve for the 4.6V stress (black) after burnin is shifted upwards compared to the curve in blue at 3.3V, which represents the time zero stress.
The slope of this line is called the ‘powerlaw slope’, . It is technology dependent and typically ranges in value from 0.15 to 0.30 [1]. The low value of n (n 1) gives rise to the ‘quasisaturating’ behaviour. It is important to note that NBTI degradation has been shown to follow a power law time dependence due to the physics of the electrochemical reaction/diffusion reaction underlying NBTI degradation [1]. Therefore, the functional form is not merely a curvefitting exercise but rather a necessary consequence of the degradation physics.
We measured the same five key DAC parameters as in the simulation. These measurements were taken after the last burnin readout of 168hours under a severe stress condition at 4.6V. A 168 hour burnin at 95% is equivalent to 7 years of normal operating condition, as in the reliability simulation. The key test results measured before and after burnIn stress are summarized in Table 5. The changes in the parameters after the burnin are comparable to those resulting from the reliability simulation, Table 3. We can therefore be reasonably confident that the ageing simulation and the emulation of ageing through burnin are consistent. In other words, we have a strong correlation, but we cannot prove causality.
Based on the test results measured, the gain error measurement after the post burnin stress was the only parameter that has a significant spike as compared to the rest of the key parameters. A significant increase in the gain error of 43.5 was observed. The ideal situation is that the DAC’s gain error has to be zero. The gain measurement was collected on the ATE tester. The pre burnin is assumed to be an ideal case with zero gain error. Table 4 shows that as the DAC input code increases, the output voltage increases accordingly to 2.5V (V).
Input code  Vout @ pre BurnIn  Vout @ post BurnIn 

0  0.000  0.000 
1  0.167  0.239 
2  0.333  0.478 
3  0.500  0.717 
4  0.667  0.956 
5  0.833  1.195 
6  1.000  1.434 
7  1.167  1.673 
8  1.333  1.912 
9  1.500  2.151 
10  1.667  2.390 
11  1.833  2.629 
12  2.000  2.868 
13  2.167  3.107 
14  2.333  3.346 
15  2.500  3.585 
The post burnin Vout was measured at the ATE tester and the Vout values increased by 43.5 compared to the typical gain error percentage of less than 20. The gain was calculated as A= 3.585/2.5 = 1.43406667. Hence, the gain error percentage is 43.5. Figure 6 shows the DAC transfer functions of ideal (pre burnin) vs actual DAC (post burnin).
In this specific case, the gain error has created a span greater than the desired ideal case. The transfer function is modelled as a typical straight line as commonly described by y = mx + c equation, where:

y is the output of the DAC

m is the slope of the transfer function

x is the input of the DAC

c is the offset voltage
Typically, an ideal DAC has a gain, m, of 1 and an offset, c, of 0 and hence the output tracks the input in a precise linear manner. However, for the real DAC, it has nonideal gain and offset values which normally can be compensated once the values are determined.
For the data taken in this burnin experiment, the design is based on an 8bit DAC with a 0V to 2.5V nominal output span. When the digital input is set to a full scale, a 3.585V output is measured.
From this data, the actual gain error, measured in percentage, can be determined by multiplying the output voltage at post burnin by the output voltage at pre burnin, 3.585V/2.5V = 1.43406667. The gain error is calculated with the assumption that the offset error is zero while the span error is measured at 850 mV, giving an actual span of 3.585V.
Notice, however, the significant increase in the gain error of 43.5. In other words, the standard reliability simulation tool correctly predicts changes in key DAC parameters, including the effect of NBTI, but appears to underestimate the change in the gain error. It is wellknown that mismatch between current mirror paired devices will cause such gain errors [14]. Therefore, it is reasonable to conclude that the increase in gain error after burnin has resulted from transistor pairs becoming mismatched, and such a mismatch is likely to be due to changes in the threshold voltages. As has been shown, above, NBTI causes significant changes in . Therefore it is again reasonable to conclude that the change in gain error, as a result of burnin, has been caused by NBTI.
Items  Pre BurnIn  Post BurnIn  Percent Change 

DNL mean  0.185 LSB  0.197 LSB  6.48% 
INL mean  0.235 LSB  0.246 LSB  4.68% 
Gain Error  2.500V  3.585V  43.50% 
Offset Error  0.000344V  0.000361V  4.90% 
Output Current  5.9 mA  6.02 mA  2% 
8 Conclusion
The NBTI degradation observed in the reliability simulation of a DAC circuit revealed that under a severe stress condition such as a 40% increase in the nominal voltage supply, a significant voltage threshold mismatch, beyond the 2 mV limit, was recorded. A burnin experiment on the DAC circuit was performed to verify the simulation. A correlation between the simulation results and the burnin behaviour was observed, but the change in the gain error was significantly greater than predicted.
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