DeepAI AI Chat
Log In Sign Up

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators

by   Gabriele Montanaro, et al.
Politecnico di Milano

In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize post-quantum cryptosystems, aiming to assess their security and speed up their adoption in production scenarios. Several hardware and software implementations have been proposed for each candidate, while only a few target heterogeneous platforms featuring CPUs and FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to timely deliver the hardware accelerators. In contrast to state-of-the-art solutions targeting performance-optimized HLS accelerators, the proposed solution targets the small FPGAs implemented in the heterogeneous platforms for embedded systems. Compared to the software-only execution of BIKE, the experimental results collected on the systems-on-chip of the entire Xilinx Zynq-7000 family highlight a performance speedup ranging from 1.37x, on Z-7010, to 2.78x, on Z-7020.


page 1

page 2

page 3

page 4


An Evaluation of the State-of-the-Art Software and Hardware Implementations of BIKE

NIST is conducting a process for the standardization of post-quantum cry...

Securing Accelerators with Dynamic Information Flow Tracking

Systems-on-chip (SoCs) are becoming heterogeneous: they combine general-...

A Systematic Study of Lattice-based NIST PQC Algorithms: from Reference Implementations to Hardware Accelerators

Security of currently deployed public key cryptography algorithms is for...

Enumerating Hardware-Software Splits with Program Rewriting

A core problem in hardware-software codesign is in the sheer size of the...

Code-based Cryptography in IoT: A HW/SW Co-Design of HQC

Recent advances in quantum computing pose a serious threat on the securi...