Hardware Implementation of Fano Decoder for PAC Codes
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This paper proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture maintains a trade-off between the error-correction performance and throughput of the decoder by implementing tree search constraining methods. The performance of the proposed decoder is evaluated on FPGA and ASIC using Xilinx Nexys 4 Artix-7 and TSMC 28 nm 0.72 V library, respectively. The PAC decoder can be clocked at 400 MHz and reach an average information throughput of 15.10 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and code rate of 1/2.
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