Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings

06/03/2018 ∙ by Ye Chi, et al. ∙ 0

Die-stacked DRAM caches are increasingly advocated to bridge the performance gap between on-chip Cache and main memory. It is essential to improve DRAM cache hit rate and lower cache hit latency simultaneously. Prior DRAM cache designs fall into two categories according to the data mapping polices: set-associative and direct-mapped, achieving either one. In this paper, we propose a partial direct-mapped die-stacked DRAM cache to achieve the both objectives simultaneously, called Gemini, which is motivated by the following observations: applying unified mapping policy to different blocks cannot achieve high cache hit rate and low hit latency in terms of mapping structure. Gemini cache classifies data into leading blocks and following blocks, and places them with static mapping and dynamic mapping respectively in a unified set-associative structure. Gemini also designs a replacement policy to balance the different blocks miss penalty and the recency, and provides strategies to mitigate cache thrashing due to block type transitions. Experimental results demonstrate that Gemini cache can narrow the hit latency gap with direct-mapped cache significantly, from 1.75X to 1.22X on average, and can achieve comparable hit rate with set-associative cache. Compared with the state-of-the-art baselines, i.e., enhanced Loh-Hill cache, Gemini improves the IPC by up to 20 respectively.

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1. Introduction

The 3D die-stacking DRAM provides high bandwidth, low latency and large capacity, mitigating memory wall. Due to its gigascale capacity, the 3D die-stacking DRAM could not replace off-chip DRAM and has been proposed to be architected as the last level cache, referred to as DRAM cache  (Loh and Hill, 2011, 2012; Qureshi and Loh, 2012; Jevdjic et al., 2013; Chou et al., 2016). The 3D die-stacking DRAM is helpful for a lot of applications, such as peer-to-peer live streaming  (Liao et al., 2006).However the DRAM cache’s tag storage overhead caused by the large capacity of 3D DRAM makes it challenging to design high performance DRAM cache. For example, with 512 MB DRAM cache, its tag lines storage overhead is about 24 MB with 64B cache line. In order to address this issue, prior research work proposes two solutions: 1) storing tags in DRAM cache with small granularity of cache line, and 2) storing tags in SRAM with large granularity of cache line. However, they still have limitations. Co-locating data lines and tag lines in DRAM cache serializes the tag access and data accesses from DRAM cache, increasing cache hit latency. Large size cache line suffers from large bandwidth overhead, DRAM cache capacity scalability, and under-utilization of space. This paper focuses on the DRAM cache design with smaller cache line size.

Hit rate and hit latency are the two important performance metrics in DRAM-d cache designs. The Alloy Cache (Qureshi and Loh, 2012) was proposed to merge a data line with its tag in tag-and-data unit(TAD) and performs tag look up by issuing a CAS command to stream out a TAD. In this way, the tag-then-data serilization has been elimiated, reducing hit latency. However, TAD restricts cache organization to be direct-mapped cache and suffers from lower hit rate. LH Cache   (Loh and Hill, 2011, 2012) architects the DRAM cache as set-associative cache by co-locating the tags with data blocks in the same row and achieving high hit rate. On serving a request, the DRAM cache controller needs to retrieve all tag lines belonged to a set by issuing a CAS DRAM command and multiple bus bursts before determining the location of the requested data line. This tag access latency increases the hit latency. Ref.  (Huang and Nagarajan, 2014; Hameed et al., 2014) proposed to cache tags in a small on-chip SRAM to speed up the tag lookup for the set-associative DRAM cache. On tag-cache hit, the data block can be fetched from DRAM cache without accessing the tag in DRAM cache. However, on tag cache miss, the tag is fetched to the tag cache before the data block is accessed. Therefore, the tag-then-data access serialization can not be completely removed from data access path by using tag cache, resulting sub-optimal performance. These research work on the DRAM cache as the directed-map cache and set associative cache exclusively and failed to optimize the hit latency and hit rate simultaneously.

We have made some interesting observations on the set associative cache with tag cache in SRAM. On the tag cache miss, a batch of tags will be fetched from the DRAM cache into the SRAM tag cache before the requested data is accessed in DRAM cache. The target data block in the first access of this set is refereed to as the leading block, and the rest are referred to following blocks. Our experimental results demonstrate that the individual blocks exhibit the stable block type, which is either a leading block or following block. Furthermore, we observed that it is the leading block that incurs the tag fetching overhead, while the following blocks can benefit from the fast tag lookup in SRAM. Our experimental results on 18 workloads (Section 5) show that on average 89% tag fetching are triggered by the leading blocks, and these tag fetching increase the leading block’s hit latency by 1.7X-2.3X compared with the direct-mapping cache. If applying direct mapping to leading blocks, their hit latency could be significantly reduced. In addition, most following blocks hit tag cache and over 97% of their hit latency is caused by the data fetching from DRAM cache, enjoying the free ride provided by the leading blocks tag fetching.

Motivated by the above key observations, we propose Gemini, a partial direct-mapped DRAM cache that exploits block differentiation with the hybrid mapping policy to achieve low hit latency and high hit rate simultaneously. Specifically, we apply static mapping to leading blocks to reduce cache hit latency, and dynamic mapping for following blocks with hit rate degradation. Geminifaces two challenging issues. First, we find that leading blocks and following blocks have different miss penalty in terms of latency and bandwidth. For example, a leading block miss incurs a latency of 273 cycles, which is 1.3X higher than that of a following block. This phenomenon should be considered in the design of cache replacement policy. Second, the frequent block type transitions are needed to handled to avoid hurting performance in some workloads.

The main contributions are summarized as follows.

  • We observe that data blocks are classified to be leading blocks and following blocks and the individual data block possess the stable block type. Furthermore, two types of data blocks have distinct impacts on the hit latency and hit rate of DRAM cache mapping policies.

  • We propose a partial direct-mapped DRAM cache, called Gemini, which applies static and dynamic mapping to leading and following blocks, respectively, to achieve low hit latency and high hit rate simultaneously. In addition to the novel mapping scheme, we also propose a cache replacement policy called Range-Variable CLOCK (RV-CLOCK) considering the different miss penalties for data blocks with different block type. Furthermore, to deal with the frequent block type transitions, we propose the priority reservation mechanism with a high frequency variation filter.

  • Through extensive evaluations, we demonstrate that Gemini cache can narrow the hit latency gap with direct-mapped cache significantly, from 1.75X to 1.22X on average, and can achieve comparable hit rate with set-associative cache. Compared with the state-of-the-art baselines, i.e., Loh-Hill cache enhanced with tag cache, Gemini improves the IPC by up to 20% respectively.

The rest of this paper is organized as follows. we present the background in Section 2 and motivations in Section 3. Section 4 introduces system design. Experimental methodologies are given in Section 5, followed by evaluations in Section 6. Related works are summarized in Section 7. Section 8 concludes this paper.

2. background

2.1. DRAM Cache Organizations

Similar to the conventional SRAM cache, DRAM cache has tag and data for each data block. Since the large DRAM cache makes it impractical to accommodate the correspondingly large tag in SRAM, LH Cache proposes to store the tag and data in the DRAM cache. LH Cache architects DRAM cache as a set associated cache by storing tag and data of a set in one DRAM row. The set-associative can reduce the conflict misses and benefit system performance. To service a request, the DRAM cache controller checks the tag and then reads the data line according to the outcome of tag query, shown in the Fig. 1, increasing the hit latency. This serialization of tag access and data line access increases the hit latency in DRAM cache, resulting in sub-optimal performance. In order to address this issue, the Alloy Cache proposes to trade the low hit latency for the low hit rate. The Alloy cache organizes the DRAM cache as a direct-mapped cache and combines a data line with its tag line, referred to as tag-and-data units(TAD). This merging of data line and tag line removes the searching correct way from the data access path and directly accesses the TAD to avoid the serialization of tag and data access depiected Fig. 1. However, it suffers from the low hit rate because of the direct-mapped cache organization. Caching tags in small size on-die SRAM  (Jevdjic et al., 2013; Chou et al., 2015; Gulur et al., 2014) was proposed to mitigate the issue of tag-then-data serialization. On a tag miss, the tags of a set are fetched in batch to the on-chip SRAM. Due to the spatial locality, the later accesses to the same set result in tag cache hit and the DRAM cache can directly access the data in the DRAM cache, without probing tag in the DRAM cache.

Figure 1. basic organizations of set-associative cache and direct-mapped cache

2.2. Access Latency Breakdown

Figure 2. Latency breakdown of direct-mapped cache and set-associative cache

Figure 2 illustrates the access latency of the set associative DRAM cache and directed-mapped DRAM cache. The direct-mapped cache can offer the lowest hit latency by fetching tag and data with a single request on DRAM cache hit (cases and ). However, if the tag cache and the DRAM cache are both missed (case ), an extra cache probe must be performed, before accessing off-chip memory. If the tag cache indicates that the data block is not present in DRAM cache (case ), the request will be directly sent to off-chip memory. On tag cache miss, the set-associative cache suffers the cache probe latency even if the request can hit DRAM cache (case ). For the rest of the cases (cases , , and ), the set-associative cache acts in the same way as the direct-mapped cache, thus have similar access latency. The benefits of the direct-mapped structure lies in low DRAM cache hit latency, but the performance is sensitive to cache hit rate. The tag fetching introduced in the set-associative cache makes the DRAM cache hit latency close to the off-chip memory, negating the benefit of DRAM cache, as show in Figure 2.

3. motivation

3.1. Leading Blocks and Following Blocks

We first define several terminologies that will be used in the rest of this paper. A section is defined as a continuous logical address region mapped to a single cache set and hence data blocks in the same region are mapped to the same cache set. This mapping enable us to preserve the spatial locality exhibited in workloads. There could be multiple sections mapped to the same set. For example, the data blocks in section A and section B reside in the same set, shown in the Fig. 3. Although this mapping is inferior to the conventional mapping in high level caches, our experimental results show it achieves the hit rate close to the conventional mapping in of DRAM cache, due to the weak locality. Each L3 cache miss checks the tag cache before proceeding to DRAM cache. On a tag cache miss, all tags in the target DRAM cache set, referred to as tag batch, are fetched to the tag cache in SRAM. A section is active if any of its tags is cached in the tag cache, or is currently being fetched. Otherwise, it is inactive. A leading block is the block to make the corresponding section to transition from inactive state to active state, and the following blocks are ones accessed later until the section becomes inactive, which is caused by tag cache replacement. In other words, a leading block is the data block experiencing tag cache miss and the subsequently accessed blocks in the same section are following blocks when their tags are in the tag cache.

Figure 3. Leading and Following Data Blocks in a Set

We use a simplified example to explain the leading blocks and following blocks shown in Fig. 3. Assume that there are eight data blocks from the section A and the section C in the same DRAM cache set, and their tags are not in tag cache. Accordingly, these two sections are in inactive state. We further assume section A has one leading block A1 and section C has two leading blocks C3 and C6. At the case 1 with the access sequence of C3, C4 and C5, the C3 is a recurring leading block, because it misses the tag cache. After the C3 being served, the set’s tag has been fetched to the tags cache, and the subsequent accesses to C4 and C5 hit tag cache. They are following blocks. The case 2 shows the new leading block, C5, in the section C because its access misses the tag cache, explaining the existence of multiple leading blocks for a section. At the case 3, the block A2 is a following block because the block C4 has activated the section A. The case 4 presents that the block C7 is also a following block even its tag is not in tag cache due to DRAM cache miss. This is because its section C has been activated by the C6.

3.2. Block Type Stability

We measure the ratio of blocks that have data type transitions for 10 workloads and they are decreasingly ordered by the transition ratio shown in Figure 4. The average ratio of block type switches is less than 0.05. These results demonstrate that block types are almost stable. The reason why blocks have stable type is that each section contains data objects accessed by the specific code and the inherent semantic of the code manipulates these data objects with its unique pattern . For example, a field variable var in a struct is accessed by the specific function before other field variables in the struct variable, which is most likely in the same region. Next time, the execution of this function repeats the same access pattern on the struct variable. In this case, the data block containing the variable var is a stable leading block. We are going to exploit the block type stability to optimize DRAM cache design.

Figure 4. The ratio of block type switches

It is worth to note that the workload R7 and R6 have non-negligible data type switches and these unstable blocks make our proposed optimization ineffective. We will discuss how to address this issue at the next section.

3.3. Impacts of Leading Blocks and Following Blocks

Set-associative cache offers high hit rate, but incurs large hit latency. In the DRAM cache, the large associativty necessitates the tags co-located with the data blocks in the same row and tags are accessed before data blocks. Such serialization of tag and data blocks is the root reason for the large hit latency.

Tag cache in SRAM is an effective way to reduce the hit latency in DRAM cache. Upon a tag cache miss, all tags of the set are fetched from the DRAM cache and then are stored in SRAM to accelerate the tag lookup for following accesses. Due to spatial locality, most of following accesses benefit from the quick tag lookup in SRAM, avoiding tag fetching from DRAM cache, because the leading blocks take the responsibility to fetch tags to tag cache.

Our experiments show the proportion of tag fetching caused by the leading blocks and the following blocks in Figure 5 for 10 workloads (details in Table 4). We find that on average 89% tag fetches are triggered by the leading blocks. Therefore, 89% the serializations of data and tags accesses are caused by the leading blocks in the setting of tag cache and hence removing these serializations could effectively reduce the hit latency. This observation motivates us to apply the direct mapping to the leading blocks. Without tag probation latency, the direct mapping can remove 89% tag-then-data serializations, reducing the hit latency.

Figure 5. Distributions of tag fetches

Differing from leading blocks, most following blocks involve only data fetching from DRAM cache since their tags are cached in SRAM. Our experimental results show that 97% of following block hit latency is caused by the data block fetching. Therefore, direct mapping can hardly further reduce hit latency for following blocks. Moreover, direct mapping seriously hurts hit rate. The above observations motivate us to apply dynamic mapping for following blocks to achieve higher hit rate and smaller hit latency.

3.4. Block Miss Penalties

Figure 6. Miss Penalty Comparison between Leading Block and Following Block

The Fig. 6 compares the miss penalty of leading block with following block. The left half of the Fig. 6 shows the DRAM cache hit and miss for the leading block. Since the leading block is statically mapped to the DRAM cache, the DRAM cache controller directly fetch the requested leading block from the DRAM cache, requiring one 3D DRAM access. After reading the leading block from DRAM cache, the cache controller detects the cache miss and fetches the tag batch from DRAM cache and the requested data block from off-chip DRAM simultaneously, shown in the bottom of the Fig.6. This figure clearly shows the miss penalties of the leading block are a data block access from off-chip DRAM in term of latency. The right half of Fig. 6 shows miss penalty for the following block is the access latency difference between the DRAM cache and off-chip DRAM. For the following block, the cache controller can quickly determine the cache miss/hit with the help of the tag batch in the SRAM. Upon hit, the requested block is fetched from the DRAM cache. Otherwise, one off-chip DRAM access is involved. Therefore, the leading block has larger miss penalties than following block in term of both latency and bandwidth consumption.

Our experimental results support the above analysis. Table 1 shows the average latency, as well as bandwidth for both the leading block and the following block on DRAM cache hit/miss under 14 workloads. We find that the leading block miss penalty is 273 cycles with a 64-byte data transfer over off-chip DRAM, and the following block miss penalty is 112 cycles. Such miss penalty differences between leading blocks and following blocks motivates us to design a DRAM cache replacement policy to minimize leading block misses.

Leading block 185 Cache: 128
458 Cache: 128
Memory: 64
273 Cache: 64
Following block 147 Cache: 64
259 Memory: 64
112
Table 1. The miss penalty of leading blocks and following blocks.

4. design

4.1. Cache Organization

As discussed in section 3, the application of the different mappings to leading blocks and following blocks could improve the hit latency and hit rate simultaneously in the context of tag cache. This is the key idea of the Gemini. The type of the requested data blocks determines how the Gemini serves the request. For the leading block, its direct mapping enables cache controller to fetch the data from the known position in the DRAM cache set without consulting the tag and the related tag batch is also transferred to the tag cache in SRAM. In this way, the cache controller can detect the DRAM cache miss for the leading block, after checking the tag batch. In order to concurrently transfer both leading block and tag batch, the data set and the corresponding tags are stored in different banks, shown in Figure 7. For the following block, the requested data needs to consulting its tag to determine the position in the set, since the dynamic mapping is applied to the following block. The following block is most likely to hit the tag cache and is quickly streamed out from DRAM cache.

Figure 7. Organizations of Gemini cache

The organization of tag row is depecited at the top of Figure 7. A tag batch contains the tags for the data blocks stored in the corresponding cache set, which is similar to the tag batching mechanism in the previous work(Loh and Hill, 2011). Four extra bits are introduced to a tag: reference bit (A), priority bit (H), and a two-bits filter (C). The reference bit indicates the recency of the block. The priority bit denotes the block’s caching priority and also acts as the block type indicator (1 for leading and 0 for following). The filter bits monitor the transitions of block type discussed in Section 4.4.

The data row’s organization is illustrated in the middle of Figure 7. In conventional designs, the direct-mapped cache and the set-associative cache are commonly viewed as two exclusive structures. Generally, the cache associativity and the mapping policy are closely coupled: 1-way set is the direct mapping, and n-way set is referred to as the dynamic mapping. In order to support both static mapping and dynamic mapping in an unified structure, we decouple the set associativity from the data mapping policy. Gemini is basically organized in a set-associative manner. Each DRAM row has several sets and each set contains 16 data lines. Within each cache set, data blocks can be mapped via either static or dynamic mapping, depending on their block types, as shown in the Figure 7. Specifically, following blocks are installed in the set according to the replacement algorithm, while leading blocks’ positions at the set are determined by the static mapping, which is the predetermined hash function of the block address.

The layout of Gemini cache is demonstrated at the bottom of Figure 7. The DRAM rows are divided into tag rows and data rows. Tags and data are mapped to the rows of different banks to improve the bank level parallelism. The ratio between tag rows and data rows equals to . In our design, , . For illustrative purpose, we show a tag row coupling with four data rows, while the ratio is in real case .

4.2. Mapping Policy

A requested block is a currently leading block if it access the inactive section whose tags are not in tag cache at the time point. Otherwise, it is a currently following block. We apply static address mapping and dynamic address mapping to leading blocks and following blocks respectively to determine the position in the cache set. The tag of the data block has the priority bit to indicate the block type. For the leading block, the address of the request block is hashed on the predetermined function and its outcome is the position for this leading block. After getting position of the leading block, the memory controller directly retrieves the data block from the DRAM cache. It is possible that there are multiple leading blocks in the one cache set since the position depends on the request block address. In that case, position conflicts caused by the hash function could lead to eviction. For the following block, the position in the set can be determined by the probing the tags stored in the tag cache in the case of tag cache hit. Otherwise, the cache replacement algorithm determines the position to be installed in the cache set. As shown in algorithm 1, we use the to denote the position determined by the cache replacement policy.

Data type transitions are needed to be handled. The algorithm 1 shows how the Gemini handle data type transitions. For the transition to the following one, Gemini resets its priority bit (line 4,5). For the transition to the leading one, Gemini tries to migrate it to the statically mapped position (line 6-17). If the data block’s current position equals to the given static mapping (line 7-8), no migration is needed , and Gemini sets its priority bit to 1. Otherwise, i.e., two positions are not equal, one of the following actions is taken: 1) If the statically mapped position is high priority, and is recently referenced, Gemini just resets its reference bit (line 10,11), without migration. 2) In the rest cases, Gemini migrates the data to its statically mapped position, with the expectation that the data will be continually accessed as a leading block in the near future.

Input: block_address, type
1 positionGetPosition(block_address)
2 static_positionStaticMapping(block_address)
3 last_typeGetType(block_address)
4 if last_type  Leading and type  Following then
5       cache[position].priority_bit0
6      
7if last_type  Following and type  Leading then
8       if position  static_position then
9             cache[position].priority_bit1
10            
11      else
12             if cache[static_position].type  Leading and cache[static_position].reference_bit  1 then
13                   cache[static_position].reference_bit0
14                  
15            else
16                   if IsDirty(cache[static_position]) then
17                         WriteBack(cache[static_position])
18                        
19                  cache[static_position]cache[position]
20                   Free(cache[position])
21                   cache[static_position].priority_bit1
22                  
23            
24      
Algorithm 1 Mapping Policy

4.3. Replacement Policy

As discussed in section 3, leading blocks incurs more DRAM cache miss penalty than following block in terms of latency and bandwidth. The cache replacement algorithm can improve DRAM cache performance by exploiting this observation. The replacement algorithm assigns high caching priority to leading blocks and low priority to following blocks. To this end, the priority bit for each data block is introduced. The priority is set to to be 1 and 0 for the leading blocks and the following blocks respectively. In this way, the replacement algorithm attempts to keep the leading blocks in cache longer to amortize its miss penalty. However, the leading blocks can gradually encroach the cache space of the following blocks due to the high priority. This intensifies the cache space competition with the following blocks. On the other hand, the cache space occupied by the cold leading blocks lead to lower cache utilization without considering the overall cache hotness.

To balance the miss penalty and cache hotness, we propose the Range-Variable CLOCK (RV-CLOCK) algorithm, which is based on the CLOCK algorithm due to its close approximation of LRU (Jiang et al., 2005) with low overhead. In the CLOCK algorithm , a reference bit indicates the recency of a data block. If the reference bits of all following blocks have been set, these recently accessed following blocks are chosen as victims for the later arriving following blocks, and the cache thrashing occurs for the following blocks, hurting performance. In order to address this issue, we attempt to evict a cold leading block to increase cache allocation of following blocks. Specifically, we run the CLOCK in the scope of the whole cache set, overriding the priority settings.

1. The victim selection upon leading block insertion 2. The victim selection upon following block insertion
Figure 8. The victim selection policies

This algorithm can be implemented with low hardware cost. As illustrated in Figure 8, the following blocks’ reference bits act as a mask of the CLOCK’s working range. If the reference bits of following blocks are all set, the algorithm runs the CLOCK for all lines to choose the victim. Otherwise, the leading blocks are masked, and thus can not be evicted.

4.4. Managing Type Switching

The mapping policy works well for the data with stable block types, which is common discussed in the section 3.2

. However, there exist some workloads whose block type transitions frequently occur. Such transitions lead to larger number of data block migrations, degrading performance. Furthermore, the mapping policy mistakenly downgrades the blocks’ priority and prematurely evicts blocks. For example, if an unstable block switches from leading block to following block, the mapping policy reset its priority bit, increasing the block’s eviction probability. At the next active period of the

section , it is highly likely that this block will switch back to be a leading block. In such a case, the mapping policy untimely evicted this leading block, suffering the costly miss penalty.

To address the issue, we further study the block type stability. For a single block, the represents the number of occurrences of consecutive leading or following type. For example, consider a type sequence of { }. Their are 2, 2, 1. The larger the value of is, the more stable the block remains the same type. Our experimental results show the are not greater than 10. After examining the workload whose percentage of block type transitions is larger than 10%, we find that 88% of is not larger than 2. This implies that the type of these blocks tend to continuously change.

Motivated by the above observation, we propose a priority reservation mechanism with a frequent type transition filter to handle unstable blocks. The key idea is that we track the blocks whose types frequently change, and assign high priority to them to avoid the potential miss penalty on their transitions. As discussed early, we mainly focus on the cases with . Specifically, we use a two-bits counter to filter out these blocks. If there is a transition, the block’s counter is increased by 2. The counter is decreased by 1 for the transition. After reaching 0, the two-bits counter remains ”00” state for the transitions. Upon a type transition, Gemini identifies the block as highly unstable and assigns high priority to it if its count is not ”00”. Otherwise, this block is assigned to low priority. Note that a leading block always keeps its counter’s state. This policy eliminates the short, isolated type transitions.

5. experimental methodology

We evaluate the performance of Gemini using Gem5 (Binkert et al., 2011), integrated with detailed models of 3D-stacked DRAM and off-chip memory (Poremba and Xie, 2012). The architectural parameters are summarized in Table 2. The processor has 8 out-of-order cores with 16MB shared L2 cache. The DRAM cache is 1GB. We assume both DRAM cache and the off-chip memory have the same latency, but the DRAM cache has higher bandwidth by 8 times (bus width, channels, banks).

5.1. Cache Organizations

We compare Gemini with the following designs. The key system configurations are listed in Table 3.

 Processor Out-of-order, 3.2GHz, 8 cores
 L1 I/D Cache 32KB I-cache, 32KB D-cache,
private, 4-way, 2-cycles
 L2 Cache 16MB, Shared, 8-way, 20-cycles, non-inclusive
 Tag Cache 32K entries, 8-way, 9-cycles
 DRAM Cache 1GB, 1.6GHz (DDR 3.2GHz), non-inclusive
4 channels, 128 bits per channel,
16 banks per rank, 2KB row buffer
tCAS-tRCD-tRP-tRAS 36-36-36-144 CPU cycles
 Main Memory 16GB, 800MHz (DDR 1.6GHz)
2 channels, 64 bits per channel,
8 banks per rank, 2KB row buffer
tCAS-tRCD-tRP-tRAS 36-36-36-144 CPU cycles
Table 2. Architectural parameters
BEAR L-H Gemini
Mapping Policy static dynamic static+dynamic
Associativity 1 14 16
Replacement BAB CLOCK RV-CLOCK
Tag Prefetch neighboring tag tag batch tag batch
Write Probe DCP DCP DCP
Table 3. System configurations

Loh-Hill Cache (Loh and Hill, 2011, 2012) We enhance the Loh-Hill cache with tag cache in SRAM as a baseline, which is refereed to as enchanced-LH cache. The associativity is reduced from the original 29 to 14 with the considerations of tag batch size, for the lower tag access latency. In our implementation, the tags and the data of the same set are placed in the same DRAM row. The tags are batched in a per-set manner, and are read together in a single request.

BEAR cache (Chou et al., 2015) As direct-mapped DRAM cache, BEAR is compared with our design. It uses a Bandwidth Aware Bypass (BAB) scheme to improve bandwidth efficiency upon miss fill. The tags and the data are placed in DRAM rows in an interleaving manner. A read request fetches the data, as well as the corresponding tag and the next neighboring tag with one additional burst. To be fair, the SRAM tag caches are set to be same size for the enhanced LH cache, BEAR and Gemini. In addition, the DRAM Cache Presence (DCP) bit (Chou et al., 2015) is included in these 3 DRAM cache designs to reduce the bandwidth consumption.

5.2. Workloads

Rate Workloads
CD  R1: wupwise8   R2: lucas8   R3: gap8
 R4: apsi8   R5: cactusADM8   R6: lbm8
LD  R7: vpr8   R8: bzip28   R9: soplex8
 R10: omnetpp8   R11: astar8   R12: xalan8
BF  R13: equake8   R14: mgrid8   R15: gcc8
 R16: libquantum8
NB  R17: GemsFDTD8   R18: milc8
Mixed Workloads
CD  M1:wupwise,luca,gap,apsi,cactusADM,lbm,wupwise,lbm
LD  M2:vpr,bzip2,soplex,omnetpp,astar,xalan,vpr,xalan
BF  M3:{equake,mgrid,gcc,libquantum}2
NB  M4:{milc,GemsFDTD}4
CD+LD  M5:wupwise,gap,apsi,cactusADM,vpr,bzip2,soplex,omnetpp
CD+BF  M6:gap,apsi,cactusADM,lbm,equake,mgrid,gcc,libquantum
CD+NB  M7:lucas,apsi,cactusADM,lbm,{milc,GemsFDTD}2
LD+BF  M8:soplex,omnetpp,astar,xalan,equake,mgrid,gcc,libquantum
LD+NB  M9:vpr,bzip2,astar,xalan,{milc,GemsFDTD}2
BF+NB  M10:equake,mgrid,gcc,libquantum,{milc,GemsFDTD}2
Table 4. Workloads

We evaluate the three designs with 18 memory intensive benchmarks from the SPEC CPU2000 and the SPEC CPU2006 benchmark suites. The benchmarks are classified based on two metrics: spatial locality and cache contention. The spatial locality is measured as , where and are the amount of leading blocks’ accesses and the amount of the total accesses respectively. The cache contention is evaluated as the DRAM cache’s hit rate111The hit rate is taken from the rate mode workloads running on the direct-mapped cache..

Figure 9. Normalized IPC. The results are normalized based on enhanced-LH’s IPC.

These benchmarks can be classified into four categories: contention-dominated (CD), locality-dominated (LD), both-friendly (BF), and non-beneficial (NB). The CD benchmarks have high cache demands and good spatial locality. The set-associative cache is friendly to these benchmarks, as it can improve the cache space utilization, and benefits from the tag cache due to the spatial locality. In contrast, the LD benchmarks have high hit rate, but poor spatial locality. The BEAR works well for these benchmarks because the hit latency has been optimized. The BF benchmarks do not have much cache demand with good spatial locality. Both basic cache organizations can perform well on these benchmarks. The NB benchmarks have poor spacial locality and high miss rate, and no design can work well for them.

The Table 4 shows 28 workloads in our experiments. There are 18 workloads in rate mode (four categories, called Rate-CD, Rate-LD, Rate-BF, Rate-NB in the following results analysis), where all the cores execute the same benchmark. We also evaluate 10 mixed workloads. The intra-category and inter-category combinations are both included. For each workload, we the simulate 1 billion instructions on each core after fast-forwarding the first 10 billion instructions

6. Results

6.1. Performance

We normalize the IPC (instructions per cycle) of three designs to that of enhanced-LH Cache, and show the results in Figure 9. For Rate-CD workloads, Gemini outperforms the direct-mapped cache, BEAR, 17.5% on average and up to 33% . The speedup of Gemini mainly comes from hit rate improvement due to its dynamic mapping of following blocks. The Rate-LD workloads have poor spatial locality, which leads to high miss rate on tag cache. For these workloads, enhanced-LH Cache performs worst, as it serializes tag and data accesses. By applying static mapping to leading blocks, Gemini outperforms enhanced-LH Cache by 18% on average and up to 23%. The Rate-BF workloads have small working sets and high spatial locality, which narrows the performance gap between different designs. On average, Gemini achieves similar performance comparing with BEAR (1 vs. 1.02), and outperforms enhanced-LH Cache by 7%. The Rate-NB workloads offer low temporal locality and large working sets. None of the designs perform well on these workloads. For the Mixed workloads, Gemini consistently outperforms enhanced-LH Cache. In four out of ten combinations (M2, M3, M8, M10), Gemini achieves lower IPC comparing to BEAR, with less than 6% performance difference.

6.2. Requests Breakdown

(a) Figure 10: Read request distribution based on data access path. From left to right, the three bars in each group are the results of BEAR Cache, enhanced-LH Cache, and Gemini Cache respectively.
(b) Figure 11: DRAM cache hit rate

To investigate how data mapping policies affect cache performance, we study the read request distributions222In this study, we mainly focus on read requests, as the write requests are not in the critical path. based on data access path. As we have discussed in section 2.2, data requests can go through different paths in the cache system. Case A: the request hits the tag cache, then hits the DRAM cache; Case B: the request misses the tag cache, but hits the DRAM cache with concurrent tag and data accesses; Case B: the request misses the tag cache, but hits the DRAM cache with serialized tag and data accesses; Case C: the tag cache is hit, and the request heads directly to the main memory to fetch the data; Case D: the tag cache is missed, the request first checks the tag in DRAM cache, then fetches data from main memory.

The distributions of different cases are shown in Figure 10. The tag cache hit rate can be calculated by adding the portions of cases A and C, and the DRAM cache hit rate equals to the sum of cases A, B, and B. For clarity, we also show the DRAM cache hit rate in Figure 11.

For Rate-CD workloads, BEAR achieves relatively low hit rate because its static data mapping limits replacement flexibility. Comparing with BEAR, Gemini doubles the average hit rate, from 32% to 63%. It is important to note that, Gemini achieves the similar hit rate as enhanced-LH Cache does (the hit rate difference is less than 5%). This implies, applying dynamic mapping for following blocks can offer good replacement flexibility, and the leading blocks can be mapped statically without introducing hit rate reduction. In addition, Gemini successfully removes the majority of serialized tag and data accesses (case B), which brings 3.5% speedup comparing with enhanced-LH Cache (see figure 9).

The Rate-LD workloads have small working sets that can be accommodated into the DRAM cache. As a result, all the three designs achieve a high hit rate. However, these workloads offer poor spatial locality, which leads to an average of 72% miss rate in the tag cache, and introduces a large ratio of leading blocks. The cache system’s performance is dominated by the DRAM cache’s hit latency. As we learn from Figure 10, 70% of the cache hits involve tag fetching. For enhanced-LH Cache, all these requests need to be done in a serialized data-after-tag fashion. In comparison, Gemini localizes leading blocks at their statically mapped positions. On average, 69% cache hits are served by concurrent tag and data fetching, which is very close to BEAR.

The Rate-BF workloads’ working set can also fit into the DRAM cache, while offering high spatial locality. The tag batching mechanism helps Gemini and enhanced-LH Cache obtain 80% hit rate in tag cache. In contrast, the neighboring tag prefetching technique used by BEAR achieves 57% hit rate in tag cache. But the difference in tag cache’s hit rate cannot bring more benefits for the set-associative cache (enhanced-LH Cache), because the direct-mapped cache (BEAR) offers same latency as long as the DRAM cache is hit. On the other hand, there is still a small portion of requests need to access the tags in DRAM cache. These requests slightly degrade the performance of enhanced-LH Cache by about 8%.

The Rate-NB workloads have large working set and the poor temporal locality. This leads to a low hit rate in DRAM cache, which limits the influence of data mapping policies, thus all the three designs have the similar request distributions. In Figure 9, we observe that all the designs get the similar IPC under these workloads.

The Mixed workloads M1, M5, M6 offer optimization space in both hit rate improvement and hit latency reduction. For these workloads, Gemini improves the average hit rate by 28% comparing with BEAR, and eliminates over 95% of the serialized tag and data accesses. It outperforms BEAR and enhanced-LH Cache by 8% and 5% on average. The workloads M2, M3, M8 have high hit rate in DRAM cache (over 90%). BEAR is the best performed design for these workloads, followed by Gemini. Due to their concurrent tag and data accesses, these two designs achieve 15% and 9% higher IPC compared with enhanced-LH Cache.

6.3. The Impact of Tag Fetching Mode on Hit Latency

For LD workloads (R7-R12, M2) with poor spatial locality, the cache system’s performance is sensitive to the access latency of leading blocks. The enhanced-LH Cache is unaware of leading or following blocks and applies unified dynamic data mapping. In comparison, Gemini apply static mapping for the leading blocks. Note that both Gemini and BEAR can concurrently fetch tag and data, but the underlying mechanism is different. Gemini accesses a leading block with two parallel DRAM cache requests: one for the tag batch, and the other for the data. BEAR co-locates each tag data pair, thus the whole tag-and-data entity can be fetched in a single request (with one additional burst).

To illustrate the impact of different tag fetching modes, we show their hit latency in Figure 12. BEAR has the lowest hit latencies. In comparison, enhanced-LH Cache’s hit latency is 1.75X on average and 1.87X to the maximum. Due to the queuing delay of Gemini, not all the tag and data requests can be done at exactly the same time. As a result, Gemini’s hit latency is 1.22X comparing to BEAR. For the LD workloads, the leading blocks’ access latency directly affects overall system performance. In Figure 9, we can see that BEAR achieves 23% higher IPC (on average) compared with enhanced-LH Cache. Gemini reduces the performance gap down to 6% with its sophisticated data mapping policy.

Figure 12. Hit latency of Locality-Dominated workloads. The results are normalized based on BEAR’s hit latency.

6.4. The Impact of Hit Rate Improvement on Main Memory Queuing Delay

High hit rate benefits system performance in two-fold. Firstly, the requests that hit the cache can enjoy the high bandwidth of the die-stacking DRAM. Secondly, high hit rate can help to reduce the main memory’s access latency. Due to the filtering effect of DRAM cache, a large portion of off-chip accesses are eliminated. The reduced access frequency leads to a relatively low queuing delay on main memory.

Figure 13 shows main memory queuing delay of the CD workloads. We compare the results of BEAR against Gemini to study the impact of hit rate. From left to right, the two bars in each group are the results of BEAR Cache and Gemini Cache respectively. We also show the hit rate with red lines. As the figure shows, the low hit rate of DRAM cache makes the CD workloads suffer a severely high queuing delay. In the worst case, i.e., R3, the queuing delay contributes up to 58% of the overall memory access latency. By improving the DRAM cache’s hit rate, Gemini reduces the queuing delay by 49% on average and 78% at the maximum.

Figure 13. The impact of DRAM cache hit rate on main memory queuing delay. From left to right, the two bars in each group are the results of BEAR and Gemini.

6.5. High Frequency Type Variation Filter

Figure 14. The success rate of the High Frequency Type Variation Filter

Gemini relies on the high frequency type variation filter to track the unstable data blocks. Figure 14 shows the percentage of the identified cases with different L. As we can see, the filter has high resistance against short L. The filtering rate of L=1, 2 are 92% and 95% respectively. Meanwhile, it pass through all the segments with L.

7. Related Work

Set-associative Cache. Loh-Hill et al. (Loh and Hill, 2011, 2012) propose to organize each DRAM row (2 KB) as a 29-way cache set, which provides good replacement flexibility. The tag and data are stored in the same row, and the data is requested right after the tag read to improve row buffer efficiency. Unison Cache (Jevdjic et al., 2014) and Bi-Modal Cache (Gulur et al., 2014) increase the cache line granularity to exploit the spatial locality, and they rely on the set-associative structure to mitigate the cache conflicts.

Direct-mapped Cache. Alloy Cache (Qureshi and Loh, 2012) breaks the data-after-tag serialization by statically mapping each data block to the DRAM cache. It also combines each tag with its corresponding data into a single entity to avoid the standalone tag read request, which introduces one additional burst. CAMEO (Chou et al., 2014) improves this design by eliminating the data copy between the direct-mapped cache and the main memory. The in-memory data that mapped to the same cache line, as well as the data that currently occupies the line, are identical to each other, and contend for the cache line via swapping, instead of inserting the data copy.

These studies present different optimizations on the set-associative DRAM cache or the direct-mapped DRAM cache. In this paper, we reveal that different data blocks can significantly impact on cache hit latency, and then propose a partial direct-mapped cache design to gain both set-associative structure’s high hit rate, and the direct-mapped structure’s low hit latency.

8. Conclusion

In this paper, we have presented Gemini, a partial direct-mapped die-stacked DRAM cache. Gemini cache classifies data into leading blocks and following blocks and places them with static mapping and dynamic mapping respectively in a unified set-associative structure. The key idea is inspired by the observations that different blocks have different impact on the cache hit rate and cache hit latency. Experimental results demonstrate that Gemini cache can narrow the hit latency gap with direct-mapped cache significantly, from 1.75X to 1.22X on average, and can achieve comparable hit rate with set-associative cache. Compared with the state-of-the-art baselines, i.e., BEAR cache and Loh-Hill cache, Gemini improves the IPC by up to 33% and 20% respectively.

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