After IC circuit design and layout, it typically takes two to three months to fabricate a 12-inch IC wafer, involving a multi-step sequence of photolithographic and chemical processing steps. Among these steps, a lithography process is used to transfer an IC layout pattern from a photomask to a photosensitive chemical photoresist on the substrate, followed by an etching process that chemically removes parts of a polysilicon or metal layer, uncovered by the etching mask, from the wafer surface. Because it is hard to control the exposure conditions and the chemical reactions involved in all fabrication steps, the two processes together lead to nonlinear shape distortion of a designed IC pattern, which is usually too complicated to model. This fact gives rise to an issue so-called mask optimization, a procedure that computes an optimized photomask (or etching mask) to make the shape of the fabricated IC wafer best consistent with its source layout design.
The inevitable shape deformations on a fabricated IC due to the imperfect lithography and etching processes often cause IC defects (e.g., thin wires or broken wires) if an IC circuit layout is not appropriately designed, especially on the first few metal layers. Nevertheless, in most cases we still cannot identify such IC defects due to inappropriate IC circuit layout until capturing and analyzing the scanning electron microscope (SEM) images of metal layers after the wafer fabrication process, making the circuit verification very costly and time-consuming.
It is therefore desirable to develop pre-simulation tools, including i) a lithography simulation method for predicting the shapes of fabricated metal lines based on a given IC layout along with IC fabrication parameters, and ii) a mask optimization strategy for predicting the best mask to compensate for the shape distortions caused by the lithography and etching processes.
As for lithography simulation, there are two categories of conventional approaches: physics-level rigorous simulation and compact model-based simulation [34, 36]. Rigorous simulation methods simulate physical effects of materials to accurately predict a fabricated wafer image and thus are very time-consuming [29, 17]
. On the contrary, a compact model-based simulation method follows loosely physical phenomena to chase a faster computational speed by exploiting complicated, parameter-dependent, non-linear functions. Different from traditional methods, we aim at developing a convolutional neural network (CNN) based approach, which learns the parametric model of physical and chemical phenomena of a fabrication process directly from a training dataset containing pairs of IC layouts and their corresponding SEM images. Based on the learned network model, we can predict a fabricated wafer image more accurately and efficiently than conventional methods.
Moreover, fab-engineers usually optimize a mask pattern by iteratively modifying the layout design based on its lithography simulations. However, rule-based lithography simulations resort to linear combinations of optical computations derived from several similar yet not identical historical fab-models. This fact may make conventional mask optimization methods unreliable against new layout patterns. The simulation reliability largely relies on a rich amount of historical fabrication data in the database, which is, however, very costly because ground-truth fab-models need to be gathered by fabricating a layout pattern with all possible configurations.
The relationship among the IC fabrication process, lithography simulator, and mask optimizer is illustrated in Fig. 1, where the “OPC” block stands for optical proximity correction, a standard approach to photomask correction for compensating for the shape distortions due to diffraction or process effects as well as guaranteeing the printability of a layout pattern, especially the printability at the corners of the process window [20, 8]. As illustrated in the red dashed rectangles in Fig. 1
, the mask used in the fabrication process is a modified version of a source layout design, aiming to compensate for possible “shrinkages” in line shapes due to the fabrication to mitigate the deviation of a fabricated IC circuitry from its layout design pattern. However, traditional OPC simulations have two primary drawbacks. First, it runs simulations based on those rules and patterns already known; thus, an OPC correction may be unreliable if an unseen layout design is given. Second, not only is a single OPC simulation computationally expensive, but also the whole OPC procedure is a time-consuming trial-and-error routine that is iterated until no irregularity can be found in the OPC estimation result. Due to its high complexity, the OPC simulation is usually performed on a limited number of regions of interest (ROIs) rather than on the whole layout design to reduce computation. Take theICWB software (IC WorkBench) developed by Synopsys  for example. ICWB takes, in average, about 34 seconds to run a simulation on an layout patch with an Intel Xeon E5-2670 CPU and 128GB RAM. It will cost around 4 days to run once an OPC simulation on a layout design, and such computational cost makes a complete OPC simulation procedure impractical. It is therefore highly desirable to develop an efficient photomask optimization scheme.
Recent progress on image-to-image translation techniques makes them suitable to tackle the above-mentioned lithography simulation (i.e., Layout-to-SEM) and photomask optimization (i.e., SEM-to-Layout) problems. However, these two issues are more complicated than general image-to-image translation problems. Take Layout-to-SEM prediction for example. First of all, the domain of IC layout images and the domain of SEM images are heterogeneous. An IC layout is a purely man-made blueprint with only lines and rectangles on it, and hence it is noise-free and artifact-free. On the contrary, an SEM image is formed by the intensity of detected signal from raster-scanning the IC surface with a focused electron beam. In additional to the continuous shape distortions introduced by the lithography and etching processes, the SEM imaging process itself also suffers from several kinds of interference (e.g., scan-line noise and shading). This fact leads SEM images to a significantly different domain from that formed by layout images. Hence, this issue is essentially a cross-domain image matching and translation problem. Second, in order to predict the corresponding SEM image from an IC layout, our solution must be capable of characterizing the shape correspondence between these two domains of images. This fact raises an unsupervised cross-domain image matching problem, which usually has not been concerned in general image-to-image translation techniques, and thus it requires a more sophisticated solution, as the concerns stated in[1, 39]. Third, for mask optimization problem, it is very costly to collect a comprehensive set of ground-truth OPC-corrected photomasks, making the training of a photomask optimization network infeasible.
To address the above problems, as illustrated in Fig. 2, we propose a fully data-driven framework that comprises two CNN-based modules, namely, LithoNet and OPCNet, functionally complementary to each other. In short, LithoNet is a cross-domain simulator of the lithography and etching processes in IC fabrication, and OPCNet is a self-supervised mask optimization CNN using the prediction results of LithoNet as supervision for the purpose of OPC.
This paper has four primary contributions:
To the best of our knowledge, we are the first to formulate the Layout-to-SEM deformation prediction problem as a cross-domain image translation and correspondence problem, and we propose a two-step CNN-based framework to address it.
The proposed LithoNet-OPCNet system is computationally much more efficient than typical optical-based contour simulation scheme, while achieving comparable prediction accuracy. Therefore, our method could enable IC fabrication plants to run a full, large-scale screening on new IC layout designs. Note that the standard OPC approaches rely on sophisticated design rules and design patterns already in the database, and thus it can only examine a limited amount of areas each time.
The proposed LithoNet is parameterized with fabrication settings. Hence, it can also predict results under different fabrication conditions so as to assist fabrication plants to find the best suitable working intervals of parameters and thus be beneficial for yield-rate improvement.
The proposed OPCNet overcomes the difficulty in lack of ground-truth mask patterns. With the aid of a novel training objective function called I/O-consistency loss, the proposed OPCNet can well simulate the mask optimization process in collaboration with LithoNet.
Ii Related Work
Ii-a Virtual Metrology
In IC fabrication, virtual metrology (VM) refers to the methods for predicting wafer properties based on fabrication parameters and sensor data from equipment without performing physical measurements on the product wafer produced by a whole costly fabrication process . Since VM techniques can significantly reduce the cost of IC fabrication, various kinds of VM methods have been proposed to address the fabrication quality prediction issues. For example, as for the prediction of average Silicon Nitride cap layer thickness, regression-based VM methods were developed as surveyed in . Specifically, Susto et al. exploited the knowledge collected in the process steps to improve the accuracy of VM prediction via a multi-step strategy . In addition, the demand of VM methods also triggers the development of theoretical techniques. The method proposed in , for instance, focused on the OPC mask design problem and modeled it as an inverse problem of optical microlithography. Optical lithography is a process used for transferring binary circuit patterns onto silicon wafers, and related discussions about lithography techniques can be found in 
. Recently, people have been attempting to integrate machine learning methods with IC implementation and VM[34, 36, 13, 4, 35, 38]. For example, Yang et al. proposed a generative adversarial network (GAN) based  inverse method to estimate the optimal mask used in the fabrication process from an OPC simulation result . However, Yang et al.’s design concentrates only on the OPC-to-Layout problem, which operates in an opposite direction of our Layout-to-SEM prediction. Therefore, to the best of our knowledge, there is no existing technique focusing simultaneously on both Layout-to-SEM (lithography simulation) and SEM-to-Layout (mask optimization) image translation problems. We deem that a hybrid method of image-to-image translation or feature mapping techniques could compose a naive solution to these two prediction problems.
Ii-B Lithography Simulation
Recently, there have been lithography simulation methods developed based on machine learning techniques. For instance, Watanabe et al. proposed a fast and accurate lithography simulation by determining an appropriate model function via CNN , and Ye et al. developed a GAN-based end-to-end lithography modeling framework, named LithoGAN, to map directly the input mask pattern to the output resist pattern . Specifically, LithoGAN models the shape of the resist pattern based on a conditional GAN (cGAN) model and predict the center location of the resist pattern via a CNN model. LithoGAN has a dual learning framework, and similarly our LithoNet also adopts a dual learning framework.
As will be detailed in Section III, we formulate the Layout-to-SEM prediction as a cross-domain image-to-image translation problem in the LithoNet design. Recent image-to-image translation methods can be divided into two groups. One requires pairwise training images, e.g., [11, 32], and the other supports training on unpaired data, e.g., . The method proposed in  was based on GANs  and VAEs , but it was designed for unsupervised image-to-image translation tasks, which could be considered as a conditional image generation model. Furthermore, the Pix2pix model 
consists of a Unet-architectured generator and a “PatchGAN” discriminator. Pix2pix uses the “PatchGAN” discriminator to model high-frequencies by classifying if each patch in an image is real or fake. Therefore, it can be adopted in various applications, such as the conversion of a cartoon map to a satellite image and the conversion of a sketch to a natural image, and becomes a benchmark in this field. The Pix2pix method was further enhanced in by taking advantages of a course-to-fine generator, a multi-scale discriminator, and a robust adversarial learning objective function so as to generate high-resolution photo-realistic images. However, none of above methods addresses the shape correspondence or the deformation field between two different domains of images, and neither do other representative image-to-image translation methods, such as CycleGAN , DualGAN , Coupled GANs , and [15, 3, 9].
However, existing image-to-image translation methods are usually inappropriate for this Layout-to-SEM image translation problem for the IC-fabrication VM purpose. Because characterizing the deviations on metal lines in a product IC from their source layouts is a critical point in IC-industry, those traditional image-to-image translation methods that lack a mechanism for precisely estimating a deformation field or the shape correspondence between the layout and SEM images are not applicable to this problem. To serve the above purpose, the proposed LithoNet model performs cross-domain image-to-image translation via learning the shape correspondence between paired training images so as to output a predicted deformation map for further VM applications.
Ii-C Mask Optimization
There also exist machine learning-based mask optimization approaches. For example, the GAN-OPC method proposed in  takes source layout patterns and their OPC simulation results as training inputs, and accordingly for an input layout design, predicts a corrected photomask that minimizes the deviations on the (simulated) fabricated circuit shapes from its original design. In order to facilitate the training process and guarantee convergence, GAN-OPC involves a pre-train procedure that trains jointly the neural network and the inverse lithography technique (ILT) . After GAN-OPC converges, the obtained quasi-optimal photomask is further used as a good enough initial for further ILT operation. In addition, Yu et al.’s method can perform simultaneously sub-resolution assist feature (SRAF)  and edge-based OPC according to a DNN framework . However, both the two methods require a collection of photomask images, such as those suggested by OPC or historical data gathered during actual fabrication process, as the ground-truth dataset for training. Because it is expensive and time-consuming to collect qualified mask images, the cardinality of the training dataset forms a performance bottleneck of these two methods. To eliminate such bottleneck, powered by LithoNet, we propose the OPCNet model for mask optimization. Because OPCNet and LithoNet are the inverse function to each other, OPCNet can be trained directly by using the SEM-styled images predicted by LithoNet without the need of using expensive photomask patterns, as will be elaborated later.
Iii LithoNet: A CNN-Based Simulator of Lithography
As illustrated in Fig. 3, the proposed LithoNet consists of a CycleGAN-based  domain transfer network and a deformation prediction network. LithoNet is designed to learn how an IC wafer fabrication process deforms the shape contours of a layout pattern. It thus can simulate the fabrication process to predict the shape deformation caused by the fabrication process for further virtual metrology applications based on i) a given layout and ii) a set of fabrication parameters. One major difficulty in learning the deformation model between a layout pattern and the corresponding SEM image of its fabricated circuitry lies in the fact that they are from heterogeneous domains. Specifically, an SEM image is a high-resolution, 8-bit, gray-scaled image with deep DOF (depth of field), whereas a layout is no more than a man-made binary pattern with only rectangular regional objects on it. As a result, the goal of LithoNet is to predict the contour shapes by learning the pixel-wise shape correspondence between every paired layout and SEM images. Nevertheless, due to the poor contrast and scanning pattern noise in SEM images, it is usually difficult to capture edge contours correctly from SEM images, on which a 1-pixel-drift corresponds to a nanometer-scale displacement on real IC products. Therefore, transferring the domain of SEM images to another intermediate domain without the above-mentioned contrast and noise problems would be beneficial.
To this end, we propose a two-step framework. In the first step, we use CycleGAN  to transfer a gray-scale SEM image to an intermediate domain, where images have SEM-styled shape contours and layout-styled clear background. Then, in the second step, given a source layout along with fabrication parameters, LithoNet predicts the shape deformation due to the fabrication process. In sum, Step-I learns to remove the difference between the SEM image and its man-made binary shape so that Step-II can learn the shape correspondence between the SEM image and its original layout. In the following subsections, we will introduce our design in details.
Iii-a Step I: Image domain transfer
Because SEM and layout images are of heterogeneous domains (styles), as demonstrated in Fig. 4, we adopt an image domain transfer technique to align their domains. By removing the interference introduced the SEM imaging process, such as bias in brightness/contrast and scan-line noise in the background, via CycleGAN 
, the processed SEM image can be regarded as in the same domain as the layout. That is, the processed SEM image retains its curvilinear shape boundaries yet is binarized as if it were a layout.
To this end, we train CycleGAN using i) a set of product-ICs’ SEM images and ii) their associated segmentation masks. The second set of images can be derived by applying either advanced thresholding [26, 19], interactive segmentation [18, 31], or pseudo-background subtraction  on the source SEM images. Note that in order to guarantee the performance of domain transfer, segmentation masks with incorrect segmentation results are discarded under user-supervision. Finally, we utilize the well-trained CycleGAN to transfer source SEM images into the layout style, and these processed SEM images are further taken as reference ground-truths to train LithoNet in Step-II.
Employing CycleGAN for domain transfer has two advantages. First, CycleGAN is an unpaired image-to-image translation method, and hence it can learn the majority decision of many image segmentation algorithms, including the analysis software provided by the SEM vendor, for SEM images based on a large collection of segmentation results of different methods. Second, utilizing a ”U-net Generator” to translate images, CycleGAN is essentially a U-net-based segmentation method  supervised by its built-in ”Discriminator” through an adversarial loss, thereby suggesting a more reliable segmentation result than U-net, a state-of-the-art segmentation benchmark. Additionally, we can simply discard some rare unreliable CycleGAN segmentation results by quick human-inspection to prevent our LithoNet from learning incorrect contour correspondences.
Iii-B Step II: Shape Deformation Prediction
To learn the shape correspondence and the deformation field between SEM and layout images, LithoNet is trained by image pairs, each containing a layout and a ground-truth segmentation mask, i.e., a processed SEM image, generated in Step-I described in Section III-A.
like network that outputs a 2D dense correspondence map depicting the deformation field between the paired training images. Then, using the sampling strategy used in the spatial transformer network (STN), the warping module synthesizes a warped version of the given input layout to simulate a wafer-fabricated circuitry based on the deformation map. STN is a differentiable module designed for enabling neural networks to actively spatially transform feature maps so that neural network models can learn invariance to translation, scale, rotation, and warpings. Consequently, we adopt the sampling strategy of STN to benefit our LithoNet.
In contrast with common image generation networks like [11, 30], the advantages of LithoNet are twofold. First, LithoNet can generate and visualize a predicted deformation field, and therefore what have been learned by the network, i.e., the shape correspondences between input training image pairs, can be verified straightforwardly. Second, based on the visualized deformation field, it would be easier to identify possible impacts (e.g., defects), no matter global or local, caused by the layout and the configuration parameters during fabrication process, on the physical appearance of an IC’s metal layer. Concisely, the deformation field generated by our LithoNet is beneficial for clarifying both global and local shape correspondences between a layout and the SEM image of its product IC.
Iii-C Training Loss Functions
The training loss functionof LithoNet is primarily defined in the following form
where, denotes the reconstruction loss that measures the dissimilarity between the training ground-truth and the synthetic SEM-styled image . Meanwhile, measures the variability difference between a paired training image pair, and guarantees the smoothness of the deformation map. Finally, is used to penalize large displacements on the deformation map, and is the regression loss of fabrication parameters.
A) Reconstruction Loss:
The reconstruction loss term is defined as the loss between the training ground-truth and the synthetic SEM-styled image as follows:
where denotes the number of pixels. We derive by the following steps: i) sampling densely pixel positions on the to-be-generated ; ii) locating the correspondences of them on the input layout according to the deformation map that records the mapping relationship between pixels on onto their counterparts on
; iii) using backward interpolation to estimate the sampled pixel values on, i.e., with non-integer positions ; and finally, iv) generating an estimated via bilinear interpolation111
where and denote ceiling and floor functions, respectively. to calculate .
B) Total Variation Loss:
The total variation loss is defined as the total variation  of the signed difference between and , that is
This term is designed to align the shape contours of with those of . Without this term, the loss function might be dominated by the reconstruction loss described in (2), and consequently LithoNet would generate a bizarre synthetic image , which can produce a high overlap ratio compared with ground-truth image but has unnaturally jiggling contours. In other words, aims to retain the shape similarity.
C) Smoothness Loss
The smoothness loss is a penalty term defined as the -norm of the weighted gradient of the deformation map:
where denotes the Hadamard product, and is an edge-aware weighting matrix defined as
Note that contour edges on the input layout and the ground-truth layout-styled SEM image result in discontinuities in the deformation map . Because such discontinuities contribute to unnecessary smoothness penalty, should be suppressed appropriately according to the gradient information of both layout and SEM images.
D) Regularization Loss
The regularization loss is defined as the norm of deformation map :
This term reflects the fact that the deformation caused by wafer fabrication tends to be small, as will be discussed in Section V-C2.
E) Regression Loss for Fabrication Parameters
Because the configuration parameters of a fabrication process are continuous variables that influence the physical appearance of a wafer layer, we formulate the relationship between the fabrication parameters and the appearance of wafer layer as a regression problem. The regression loss is defined as
where is the reference IC shape segmented from the ground-truth SEM image used for training; is the fabrication parameter vector corresponding to , and respectively denote the input layout and input fabrication parameter vector for prediction, and is the predicted deformed IC shape. Therefore, this loss term aims to train i) a generator able to predict a synthesized SEM-styled image based on the given and , and ii) a discriminator able to estimate the fabrication parameter vector associated with .
Iv OPCNet: A CNN-Based Photomask Corrector Based on LithoNet
As described in Section II-C, the major challenge in developing a learning-based mask optimizer is to collect a comprehensive amount of ground-truth mask data corresponding to various layout patterns, e.g., well OPC-corrected photomasks leading to desired shapes of fabricated circuitry. This is, however, very costly and time-consuming. To overcome this difficulty, as shown in Fig. 2, we utilize a pre-trained LithoNet as an auxiliary module to train our photomask optimizer, OPCNet. Given an IC layout pattern, OPCNet aims to predict an OPC-corrected mask pattern so that, after being deformed by the lithography and etching processes that are simulated by LithoNet, the predicted deformed shape will be as close as the original layout pattern. Therefore, OPCNet can be regarded as the inverse model of LithoNet. As a result, for a desired layout pattern, we can use its predicted outputs of LithoNet as the input of OPCNet, and the desired layout itself as the corresponding output of OPCNet. Given a collection of such input-output pairs, we can train OPCNet without the need of collecting the ”ground-truth” OPC-corrected photomask patterns.
Specifically, given a layout design pattern , OPCNet aims to generate a photomask , whose lithography and etching simulation result predicted by LithoNet best matches . This design makes our OPCNet “groundtruth-free” during the training stage should LithoNet have been already well-trained. In addition, with the design of the input-output consistency loss used to measure the dissimilarity between a layout design pattern and its lithography simulation result
, OPCNet becomes an self-supervised learning method. The whole pipeline of our mask optimization method is illustrated in Fig.2. Note that i) the pretrained LithoNet is fixed while training OPCNet, and ii) OPCNet is intrinsically a generator for translating a layout pattern into its optimal photomask based on the wafer fabrication model learned by LithoNet.
Iv-a Training Loss Functions for OPCNet
The overall training loss of OPCNet is defined as
where, denotes the input-output consistency loss measuring the dissimilarity between input layout and LithoNet’s output , represents the total variation loss on the difference between and , and denotes the mask smoothness loss for ensuring the smoothness of the obtained photomask patterns .
A) Input-Output Consistency Loss:
The input-output consistency loss aims to guide the learning of OPCNet so that the shape predicted by LithoNet best matches the desired input layout , provide that the source layout is OPC-corrected by the learned OPCNet. The loss term is defined as follows:
where denotes the number of pixels.
B) Total Variation Loss:
Similar to (3), the total variation loss is defined as the total variation of singed difference between the input layout and the prediction of LithoNet .
which is again an empirical term used to avoid unnatural patterns on the predicted shapes. prevents from being dominated by the I/O-consistency loss . Without this term, the OPCNet may produce a unnatural correction.
C) Mask Smoothness Loss:
The mask smoothness loss is defined to be the -norm of the gradient of the mask prediction, that is,
This term penalizes the discontinuity on the corrected photomask to guarantee the smoothness of shape contours of . Note that does not collaborate with an edge-aware weighting matrix since there are no ground-truth masks that define true contour edges in the training dataset.
V Experimental Results
V-a Dataset and Settings
Images demonstrated in this paper are selected from two datasets provided by United Microelectronics Corporation (UMC). Both these two UMC datasets consist of pairs of images, each containing one layout image patch and its wafer’s SEM image patch. UMC dataset #1 contains SEM images taken from wafers fabricated with the same fabrication parameters, and UMC dataset #2 contains SEM images taken from wafers fabricated with seven various normalized parameter settings ranging from to . In total, UMC dataset #1 contains (i) a 942-pair training subset and (ii) a 100-pair blind testing subset, whereas UMC dataset #2 contains (i) a subset comprising pairs222there are 1,057 layouts and 7 different settings per layout, totally 7,399 pairs of images. for training and (ii) another subset comprising pairs for blind testing. All images in the blind testing set are collected from historical fabrication data; compared with those in the training sets, the blind test images are of much larger dimension and contain unseen design patterns. We trained CycleGAN for style-transfer in Step-I on UMC dataset #1, and LithoNet on UMC datasets #1 and #2. As for OPCNet, it was trained on paired data, each of which contains (i) a layout image in the first dataset and (ii) its fabricated IC shape predicted by feeding into a pre-trained LithoNet. As a result, OPCNet can be trained in an unsupervised manner. In our experiments, all image patches are downscaled from to to reduce the computational complexity. The five loss terms described in (1) are weighted empirically by .
V-B Performance Metrics
The performance of our model is evaluated objectively in terms of some widely-used similarity metrics, including Intersection Over Union (IOU), SSIM , and per pixel error rate. We will demonstrate in detail that our model outperforms other image-to-image translation methods and the standard OPC approach.
V-C1 Image domain transfer
. Obviously, the source SEM images contain typical complications from SEM imaging process, such as bias in brightness/contrast probably due to gain-shift and scanning-pattern noise. It is thus difficult for common methods to threshold an SEM image appropriately. By exploiting a well-trained translator, e.g., CycleGAN, an SEM image can be transferred into a layout-styled format with its contour shapes keeping unchanged.
V-C2 Prediction Results
Fig. 6 illustrates the deformation map predicted from the input layout, the predictions of fabricated IC shapes based on the deformation map, and the corresponding ground-truths of fabricated IC shapes extracted from their associated SEM images. The deformation maps show that LithoNet successfully learns to widen lines within open areas and to condense lines otherwise. Because such information is the key to the metrology applications, such as layout scoring and OPC simulation described in Fig. 1
, this experiment also demonstrates that LithoNet can be used to bridge computer vision techniques with both fields of semiconductor manufacturing and computer-aided-design.
V-C3 Ablation Study of Loss Terms
Here we examine and discuss the effectiveness of individual loss terms in (1). First of all, we made numerical comparisons among different loss settings in Table I and Table II, each of which corresponds to a different dateset. The results shown in Table I were derived by LithoNet trained on UMC dataset #1, whereas Table II shows the performance of LithoNet trained on a small subset of UMC dataset #1 containing 480 training patches (obtained from 16 image samples through data augmentation). From Tables I and II, we can observe that the total-variation loss, , contributes significantly to the performance improvement. Moreover, is beneficial to improve the objective performance when only a very limited amount of training samples is provided, as shown in Table II. On the contrary, as listed in Table I, contributes not so effectively to the objective performance, when a comprehensive enough training dataset is given. We demonstrate the SEM-styled images predicted according to small training dataset without using the smoothness loss in Fig. 7, where unexpected artifacts are highlighted in red rectangles. This experiment set shows the necessity of , especially in cases of a small trainingset.
The visual effect brought by the total-variation loss is demonstrated in Fig. 8, where the “Baseline” column demonstrates images derived using , whereas the “Full” column shows predictions synthesized using . This experiment set shows how improves the visual quality of synthetic SEM-styled images. Take regions highlighted by red rectangles in Fig. 8 for example. Without , LithoNet tends to produce straight-line edges and sharp corners, although there are no such patterns on the training images produced by a real IC fabrication process, as shown in “Ground truth” column. By adding to the total loss function, such artifacts can be largely mitigated, thereby more faithfully predicting the shapes of segmented SEM images.
V-C4 Comparison with Pix2pix
As LithoNet is kind of image-to-image translation schemes, we compare it with Pix2Pix , a representative GAN-based image-to-image translation method. This experiment set was designed for two purposes. One is to verify if LithoNet is able to learn special shape correspondence between layout and SEM images, and the other is to check if LithoNet is more advantageous than Pix2Pix in this regard.
As shown in Table I, Pix2pix achieves slightly higher objective metric values than LithoNet. This situation, however, lies in the fact that these objective metrics mainly reflect the effect of the reconstruction loss term solely. Nevertheless, compared to Pix2pix, our total loss function described in (1) contains several additional loss terms, including , , and , which do actually lead to better visual quality as will be explained later.
As illustrated in Fig. 9, Pix2pix produces artifacts like blurred and jiggled contour edges, whereas LithoNet is able to generate clear and smooth ones. Since both Pix2pix and LithoNet utilize -norm to guarantee a global shape similarity, this phenomenon would be probably due to the different control strategies over local shapes. Specifically, LithoNet makes use of the total-variation loss, smoothness loss, and regularization loss to control the local deformations, whereas Pix2pix relies on its discriminator architecture, the so-called PatchGAN design that penalizes a structure at the scale of patches, to handle local deformations. Consequently, because PatchGAN does not put any penalty on blurred and jiggled edges and learns only to classify if each generated patch looks realistic, such artifacts are reasonable trade-offs of Pix2pix’s PatchGAN design.
|Loss||Avg IOU||Avg SSIM||Avg Error|
|Loss||Avg IOU||Avg SSIM||Avg Error|
|Method||Avg IOU||Avg SSIM||Avg Error|
Fig. 10 compares the prediction results of feeding LithoNet and Pix2pix with test images containing significantly distinct layout patterns from those in the training image set. Moreover, the source dimension of these testing images is much larger than the training data. Therefore, through this experiment we can appraise the reliability and robustness of LithoNet and Pix2pix in mimicking an IC fabrication process when the input layout is a brand new, unseen pattern of a different scale. We can observe from Fig. 10 that, for unseen layout patterns of a different scale, LithoNet significantly outperforms Pix2pix in terms of the clarity and integrity of shape boundaries, although the predictions of LithoNet still cannot perfectly match the ground-truth for lack of suitable training samples. Finally, Table III lists the numerical comparisons between LithoNet and Pix2pix for this case.
V-C5 Fabrication parameters
Fig. 11 compares the predictions by LithoNet trained on UMC dataset #2 driven by different configuration parameter values for wafer fabrication. We focus on one configuration parameter which is normalized to the range of and is inversely proportional to the degree of etching: the larger the parameter value, the lower the degree of etching. Those parameters values used in the training dataset are colored black, whereas those values not used in training are colored red. This experiment shows that the proposed LithoNet, thank to the regression loss term described in (7), does learn the relationship between the line width and the fabrication parameter used to control the degree of etching in the fabrication process. Concisely speaking, the larger the parameter is, the wider the metal line should be. Hence, our LithoNet model is able to mimic the fabrication process and generate parameter-dependent prediction results. This is an important aspect of LithoNet design, and such design makes LithoNet suitable for semiconductor manufacturing simulations.
V-C6 Model generality
We examine here LithoNet’s range of applicability. The image pair in the top row of Fig. 12 shows that, in an open area, the general fabrication process typically produces a metal line wider than its layout design, as highlighted by the red rectangle. The predicted image shown in the bottom row of Fig. 12 tells that LithoNet learns the shape correspondence between paired training images, so it predicts a wider line in an open area and a narrower one in between two neighboring lines. In addition, the highlighted regions in Fig. 13 demonstrate that at image borders the predictions by LithoNet are different from the ground-truths. This is because, at image borders the shape deformations due to the lithography and etching processes behalf differently from those in non-border regions, but LithoNet treats them regularly. For example, LithoNet regards a line reaching a patch boarder should extend to the adjacent patch rather than shrink from the boarder. Such border effects can be easily handled by collecting enough training data at image borders along with an additional label signifying whether a region is a border one. Consequently, LithoNet can be expected to forecast fabrication results as long as a large enough amount of training data is given.
Finally, we design another experiment to show that LithoNet can well learn the ”necking” and ”rounding” effects that usually occur in IC fabrication, as highlighted by red rectangles in Fig. 14(a) and indicated by the red and blue arrows in Fig. 14(b). Necking is a high-risk pattern caused by either a tip-to-line or a line-end too close to another line on the layout design. As illustrated in Fig. 14(b), such situations may result in a line narrower than designed after fabrication. Hence, this experiment set evidences again that a well-trained LithoNet is capable of mimicking the semiconductor lithography and etching procedures.
V-D1 Impacts of Loss Functions
As described in Section IV, given a layout design pattern , OPCNet aims to generate a mask whose lithography simulation result predicted by LithoNet is best similar to . The OPCNet is controled jointly by the IO-consistency loss , the total-variation loss , and the mask smoothness loss . The former two loss terms measures the dissimilarity between and , whereas the third one focuses on the smoothness of . We here examine how and contribute to the mask prediction task.
Demonstrated in Fig. 15 are three columns of images, each of which corresponds to one loss setting. Comparing the mask predicted by using with that by , we can find that guarantees the quality of shape contour in the lithography simulation. No matter the of LithoNet or the of OPCNet, such total variation loss accounts for the difference between predicted contours and their ground-truth and focuses on pixels around the contour pixels. This term helps guarantee the similarity between the input layout and the lithography simulation and also avoid unexpected artifacts at contours. Finally, comparing the mask predicted by with that by , we find that can globally suppress unexpected artifacts on the predicted mask image. The mask prediction derived by described in (8) can thus be artifact-free and smooth.
V-D2 Mask Prediction Results
Finally, demonstrated in Fig. 16 are the masks predicted by OPCNet. Given a well-trained and accurate lithography simulator LithoNet, Fig. 16 evidences that our mask optimizer OPCNet can successfully perform the mask optimization task in a self-supervised learning manner without the need of collecting ground-truth OPC-corrected masks. With OPCNet, a layout pattern can be adequately corrected so that the resulting circuit shape best matches the source layout pattern, after an IC-fabrication process.
In this paper we proposed a data-driven framework involving two convolutional neural networks: LithoNet and OPCNet. First, given a layout for virtual metrology, LithoNet mimics the lithography and etching processes in IC fabrication to predict the shape of a fabricated IC circuitry of a given layout design. By learning the shape correspondence between paired training images, i.e., IC layout designs and their fabricated IC SEM images, LithoNet can predict the shape deformation field of the layout and then generate a lithography simulation result. Second, with pre-trained LithoNet, OPCNet can learn a mask optimization model without ground-truth OPC-corrected masks based on the proposed input-output consistency loss. Experimental results evidently demonstrate that, in the lithography simulation issue, our method is more appropriate than existing image-to-image translation schemes and outperforms the standard compact model-based simulations. In the mask optimization problem, OPCNet can correctly predict the mask that its lithography simulation image is close to the expected layout. One on-going extension of this work is to establish a scoring system, based on the deformation map or SEM-styled image derived by our method, so that a virtual metrology system for IC circuit layout quality assessment can be developed.
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