Neural network model pruning is a commonly used technique to make deep learning inference fast and memory-efficient [1, 2, 3, 4]. It identifies non-critical parameters and removes them from a baseline model such that the pruned model has reduced computation and memory costs. This pruning procedure takes millions of iterations that repeat the process of pruning and retraining [5, 6, 4, 7] or pruning while training [8, 9, 10, 11]. We find that commonly used deep learning training accelerators with large systolic arrays [12, 13, 14]
are inefficient in processing these (intermediate) pruned models, which decrease compute unit utilization by 60% in training and pruning modern convolutional neural network (CNN) models. This is true even for structured pruning, which removes parameters at the granularity of semantic groups (e.g., channels or network layers) such that the pruned models remain dense and do not require complex sparse data indexing that limits practical performance gains with arbitrary pruning[11, 15]. To overcome this inefficiency of underutilized resources, we introduce FlexSA, a flexible systolic array design that can reconfigure its structures at run-time to better fit the specific and dynamic workload of pruning DNN models and overcome the inefficiency we observe with standard systolic arrays.
Structured pruning removes parameters at the granularity of semantic groups (e.g., channels or network layers) and the pruned models remain dense, yet have fewer parameters. This pruning takes millions of iterations that repeat the process of pruning and retraining [5, 6, 4, 7] or pruning while training [8, 9, 10, 11]. We find that commonly used deep learning training accelerators with large systolic arrays [12, 13, 14] are inefficient in processing these (intermediate) pruned models, which decrease compute unit utilization by 60% in training and pruning modern convolutional neural network (CNN) models. To overcome this inefficiency, we introduce FlexSA, a flexible systolic array design that can reconfigure its structures at run-time to better fit the specific and dynamic workload of pruning DNN models and overcome the inefficiency we observe with standard systolic arrays.
The execution inefficiency without FlexSA is mainly found in processing matrix multiplications and accumulations, which account for more than 95% of the operations in modern deep learning models [16, 17, 18, 19]. These matrix operations are commonly executed as general matrix multiplies (GEMMs)  using high throughput training accelerators. For efficient acceleration of these GEMMs, many modern training accelerators adopt large systolic array cores that are (typically) a two-dimensional mesh of many simple and efficient processing elements (PEs) [12, 21]. Because GEMM dimensions in model training are both large and multiples of the typical systolic array sizes, tiling and processing these GEMMs can fully utilize PEs on systolic arrays. This is shown in Figure 1.a, where the two arrays of gray boxes are input matrices for a tiled GEMM and each red box in the systolic array indicates an active PE.
However, the GEMM dimensions during structured pruning gradually and arbitrarily shrink. Thus, the tiles at the edges of an intermediate pruned GEMMs are not divisible by the size of a systolic array as shown in Figure 1.b. Processing these small GEMM tiles does not fully occupy the PEs (white boxes), which significantly decreases the performance. This problem is also known as tile quantization, which seriously degrades performance in DNN training using GPUs . Splitting a large systolic array into multiple small arrays can improve PE utilization (Figure 1.c). However, this naive core splitting requires broadcasting inputs to multiple cores. This input replication increases on-chip data traffic, decreasing the energy-inefficiency of training and pruning.
To achieve both the high on-chip reuse of using a large systolic array core and the high PE-utilization of using many-small cores, FlexSA uses a core with four systolic arrays as the baseline. It adds input and output data paths between the four small cores and their control logic that incurs only 1% area overhead. These design changes enable forming four different systolic array operating modes, which support inter-core collaborative and per-core individual systolic dataflows. These FlexSA modes improve input and output reuse by sharing them between cores, which makes FlexSA modes efficient in dealing with GEMM tiles with different sizes and shapes.
For efficient utilization of the flexible systolic array resources, we propose a compile-time GEMM tiling heuristic. The proposed heuristic prioritizes FlexSA modes that have high inter-core reuse. The FlexSA modes with limited inter-core reuse are chosen only when using them improves PE utilization. Our data shows that this compile-time technique uses inter-core systolic dataflows more than 89% of the time without decreasing PE-utilization while pruning and training popular modern CNN models. The FlexSA compiler also handles loading inputs to input buffers then to registers and storing GEMM outputs to on-chip global buffers or DRAM at static time according to the type of FlexSA modes. Overall, the proposed FlexSA architecture increases PE utilization by 37% compared to a large systolic array design and improves on-chip data reuse by 1.7X and energy efficiency by 28% compared to a naive many-small-core design.
To summarize, our main contributions are:
We show that commonly used high throughput training accelerators with large systolic arrays are highly inefficient in processing structured model pruning due to reduced PE utilization.
We show that naively splitting a large core into many small cores decreases energy efficiency due to reduced on-chip reuse and performance of pruning because of increased memory bandwidth peaks.
We propose FlexSA, a flexible systolic array architecture that restructures its core structure to support multiple systolic array operating modes for efficient processing of GEMM tiles with different sizes and shapes.
We propose a compile-time GEMM tiling heuristic that tiles GEMMs into parts that best utilize FlexSA resources. FlexSA with our proposed GEMM tiling heuristic achieves both high data reuse of using a large core and high PE utilization of using multiple small cores.
In this section, we briefly discuss the background on deep learning applications and training accelerator architectures needed to understand the challenges we focus and our proposed ideas for them.
Ii-a Network Model Training and Pruning
Deep learning applications consist of many layers that have millions of weights (or learning parameters) to learn complex features from a large training dataset. Training needs forward and back-propagating the training dataset through network layers repetitively, which involves trillions of FLOPs (floating-point operations) and memory accesses. Most of these FLOPs are matrix multiplications and accumulations and they are typically processed as GEMMs for simple and efficient processing on high-throughput training accelerators. Training generally uses large mini-batch sizes (a set of input samples propagated at a time per training iteration) thus the GEMMs in training have large data parallelism in all dimensions [23, 24].
Model Pruning Methods. Model pruning has been studied primarily for CNNs (convolutional neural networks), to make their models more compact and their inference fast and energy-efficient. Pruning methods compress a CNN model by removing non-critical (or small-valued) weights by identifying such weights during training [9, 11] or after training using a pre-trained baseline model [5, 6, 4, 7]. They gradually remove non-critical weights by repeating the process of pruning and re-training to minimize its impact on accuracy. Recent prior work prunes weights during training to save not only the cost for inference but also for training [8, 10]. They regularize weights to small values then prune the weights whose absolute values are under a small threshold. For both approaches, pruning happens gradually thus training accelerators have to deal with both the baseline model and (intermediate) pruned models.
These pruning algorithms can be unstructured or structured. Unstructured (or individual-weight) pruning can maximize model-size reduction but requires fine-grained indexing with irregular data access patterns. Such accesses and extra index operations lead to poor performance on deep learning accelerators with vector or matrix computing units despite the reduced number of weights and FLOPs[25, 26, 27].
On the other hand, structured-pruning algorithms remove or reduce fine-grained indexing and better match the needs of hardware and thus effectively realize performance gains. Channel pruning is the most commonly used structured pruning technique for CNNs [5, 11, 7, 28, 8, 29, 30]. It removes weights at the granularity of channels. This reduces one of three GEMM dimensions (width, height, and depth) of each convolution layer reducing its data parallelism.
Ii-B Systolic Arrays
Training accelerators are designed to minimize training time thus requires high compute throughput. To efficiently process GEMMs in training workloads using a large number of PEs while avoiding redundant memory accesses, many modern training accelerators (e.g., Google’s TPU , Intel’s Nervana NNP , and Tesla’s AI chip ) adopt systolic arrays. A systolic array (Figure 2) is a two-dimensional mesh of many simple and efficient PEs. At each cycle of kernel execution, each PE applies the same computation to its inputs and then passes the computed result or its unmodified inputs to one or more of its neighbors. All PEs communicate only with adjacent PEs such that there is minimal data movement and high computational concurrency . A GEMM is tiled such that each tile is processed fully within the systolic array. Ideally the tile is sized to exactly fit the array and fully utilize its PEs. Tiles are scheduled according to a fixed systolic dataflow. Input- and output-stationary systolic dataflows are the most commonly used ones and achieve high in-core input and output reuse, respectively .
Computation of systolic dataflows consists of pipelining inputs from the top and left edges of the array (in our example) and obtaining results at each PE or at the bottom of the array depending on the dataflow type. Figure 2 shows the operation of input-stationary dataflow, where one of the two input matrices for a GEMM tile is pre-loaded at each PE then the other input matrix is shifted horizontally. Executing a GEMM tile is further blocked by the local input buffer size, processing m at a time. We call this blocked systolic computation batch a systolic wave.
Iii Architectural Challenges of
Channel pruning is done by retraining a pre-trained dense model or pruning while training from scratch. In both cases, training accelerators have to deal with both dense and (intermediate) pruned models. Unlike unpruned models that typically have a regular number of channels, such as 64, 128, or 256 (powers of two) [33, 34, 35], their channel-pruned versions have an irregularly reduced number of channels (e.g., 3, 71). The GEMMs converted from such channel-pruned convolution and FC (fully-connected) layers also have severely reduced sizes. Tiling such GEMMs to large systolic array cores can be inefficient: many GEMM tiles have sizes smaller than the size of a large systolic array (e.g., 128128). Thus processing these tiles does not fully utilize the PEs in the systolic array. This causes severe compute resource underutilization and limits training time saving even with large FLOPs reduction by continuous pruning.
To show the low efficiency of a large systolic array for training pruned CNN models, we prune ResNet50 , the most commonly used CNN model for image classification, while training. We use the WaveCore training accelerator, discussed by Lym et al. , which executes GEMM tiles using 128128 systolic arrays using the input-stationary dataflow, similar to Google’s TPU v3 . We use PruneTrain, which regularizes parameters in each channel to zero as a mechanism to prune channels during training . Figure 3 shows the execution time per training iteration over the process of pruning-while-training using WaveCore. Each bar shows only the sum of convolution and FC layer execution time considering that they account for
98% of the FLOPs in a training iteration. The training iteration time is normalized to that of the baseline before pruning. In this experiment, we use a pruning interval of 10 epochs and the two figures show the results of using different pruning strengths as introduced in PruneTrain: low pruning strength that removes relatively few channels with only a small accuracy loss (top), and high pruning strength that removes more channels with a larger accuracy loss (bottom). We evaluate this using an instruction-level simulator that we develop.
The figures show two bar graphs: the blue bars (IDEAL) indicate the execution time with the assumption of 100% PE utilization and the red bars (ACTUAL
) show the increased execution time caused by PE underutilization. All bars are normalized to the execution time of the unpruned baseline (the left-most red bar in each figure). The black line in each figure indicates the PE utilization at each pruning interval. The PE underutilization is solely caused by the size mismatch between GEMM tiles and the systolic array and is estimated with ideal (infinite) memory BW.
As the blue bars show, PruneTrain gradually reduces the FLOPs of the unpruned baseline model to 48% and 25% when using the low and high pruning strengths, respectively. However, due to the large systolic array size and reduced GEMM dimensions in many convolution layers, PEs become highly underutilized as pruning proceeds and exhibit overall PE utilization of only 69% and 58% for the low and high pruning strengths, respectively. Also, even the baseline model shows only 83% PE utilization and this is because some early convolution layers have a small number of channels.
Iv Naive GEMM Core Splitting
Diminishing PE Utilization and Increasing Input Load Cost. The PE underutilization caused by small GEMM dimensions can be mitigated by splitting a large systolic array core into multiple small cores. GEMMs can be tiled into smaller parts then executed with higher PE occupation on the smaller cores. However, this many-small-core design can be inefficient in processing large GEMM tiles, which still account for most GEMM tiles in both pruned and unpruned CNN layers. First, small cores have low in-core input reuse compared to a large core, which increases input traffic from memory or the global buffer. Second, having more cores increases the area complexity of wires, data path switches, and SRAM buffer control and decoding logic.
To study the relationship between the core size and PE utilization, we conduct an experiment that estimates overall PE utilization and the volume of on-chip data traffic while pruning ResNet50 during training with PruneTrain. The baseline accelerator design used in this experiment has a group of systolic array cores sharing one global buffer (GBUF) (Figure 5.a). The GBUF is used to block GEMM inputs and share them among cores. The evaluation is done with different core configurations, which are the points on the X-axis of Figure 5 indicating corescore size. This baseline design also has a pair of local buffers (LBUFs) in each core for input double buffering to hide input load latency. The blue lines in Figure 5 show PE utilizations and the red lines show the average data traffic volume between the GBUF to LBUFs when using low (solid lines) and high (dotted lines) pruning strengths. Both PE utilization and data traffic volume are averaged across training iterations over the whole training run, thus they encapsulate the results of the baseline unpruned model and many different intermediate pruned models. We use ideal memory BW to show the PE underutilization caused solely by the size mismatch between GEMM tiles and the core.
Splitting one 128128 core into four 6464 improves PE utilization by as much as 23% but it also increases input load traffic by 1.7 due to reduced input reuse. Further splitting the cores yields diminishing PE utilization improvement but continues to increase data traffic. Using 16 (3232) and 64 (1616) cores improves PE utilization by only 8% and 4% but increases input load traffic by 3.4 and 6.6. Also, 3232 and 1616 cores show almost similar PE utilization for the two ResNet50 pruned using different pruning strengths. This indicates that small cores do not necessarily improve the PE utilization of the more aggressively pruned CNN models. Overall, this result shows that reducing the core size to less than 3232 is not cost-efficient.
High Area Overhead of the Many-Small-Core Design. The increased data traffic of small cores requires higher on-chip data BW: when the core count increases by 4, the peak on-chip data BW required increases by 2. The impact of increasing input BW is different depending on the accelerator design. Figure 5 shows two potential buffer designs. In the baseline shared buffer design (design (a)), cores share a GBUF. The distributed buffer design (design (b)), there is a dedicated GBUF for each core. A shared buffer needs additional data paths from GBUF to the LBUF for each core, along with path switches. On the other hand, a distributed buffer design has lower data path-associated area overhead but instead increases area for splitting LBUFs and GBUFs (duplicating decoding and data repeating logic). Furthermore, in the distributed buffer design, inputs should be carefully allocated to cores to avoid input replication. Although shared data can be split across cores, this leads to data transfers over potentially low-BW inter-core channels. A more general accelerator architecture mixes these two designs by creating multiple groups of cores such that cores in each group share a GBUF [37, 38].
We compare the area overhead of different core configurations that have different core sizes and buffer designs (Figure 6). For simple estimation, this experiment considers only the area of PEs, SRAM buffers, and data paths. We use CACTI 7.0  to estimate the area overhead of buffers and use the module size of a mixed-precision multiplier and adder unit  to estimate the area of the systolic array. When the number of cores becomes greater than four, we group the cores such that they share a GBUF and this configuration is shown in the second row of the X-axis (G and C indicate groups and cores, respectively). The blue line graph in Figure 6 shows the area overhead of only the additional logic for splitting GBUFs and LBUFs. The red line indicates the area overhead of increased data paths.
The overhead of data paths is estimated conservatively assuming the wires do not overlap with logic (so the actual overhead should be smaller). The increase in chip width and height from additional data paths is estimated by distributing the wires to 5 metal layers using a wire pitch of 0.22um, similar to the method used by DaDianNao . The overheads of different core configurations are normalized to the area of a single 128128 core.
Splitting a single core to 4 (6464) cores has a relatively small area overhead of 4%, and this (❶) mainly comes from doubling the data paths by having cores share a GBUF. Further splitting them to 16 (3232) cores increases area overhead to as much as 13%, where the overhead for dividing a GBUF to four parts is added (❷). Finally, 64 (1616) cores have a 23% area overhead. The additional area overhead comes from increasing the number of cores sharing a GBUF in each group. Overall, this experiment shows that splitting a large core is not scalable. Especially, splitting a core into 16 small cores is not an area-efficient design option.
In summary, naively splitting a large core into many small cores improves PE utilization but its gain diminishes as the splitting factor increases. In addition, the many-small-core design increases total traffic from the GBUF due to the reduced in-core input reuse and also requires high area overhead. To better balance these tradeoffs, a new systolic array core architecture is needed to maintain high input reuse as using a large core and achieve high mapping flexibility as when using multiple small cores.
V Flexible Systolic Array
In this section, we introduce a systolic array architecture that achieves both high PE utilization and low on-chip traffic in processing (partially) pruned CNN models.
V-a FlexSA Core Architecture
To map small GEMM tiles to cores with high PE utilization, splitting a large core into smaller cores is unavoidable. However, processing a large GEMM tile using multiple small cores is inefficient as this increases on-chip data traffic between GBUFs and cores. Especially, this becomes a critical problem as GBUF access costs grows with the size of the systolic array. To take advantage of the benefits of both a large core and multiple small cores, our idea is to use a group of small cores that collaborate when processing a large GEMM tile and work independently when processing small GEMM tiles. To this end, we propose FlexSA, a flexible systolic array architecture that meets the need for both high input reuse and PE utilization.
Figure 7 shows the logical structure of FlexSA. FlexSA is based on four systolic array cores sharing a GBUF, as illustrated in Figure 5.a. However, unlike the baseline four-core design, where each core always operates independently, FlexSA can reconfigure its operation mode such that the four cores work independently or collaboratively. FlexSA provides four different operating modes and they are supported using additional data paths and path switches (red data paths in Figure 7).
Sub-Array Operations. The four different systolic operating modes are illustrated in Figure 8. FW (full wave) uses the four cores as a single systolic array by sharing inputs and passing partially accumulated outputs between cores (Figure 8.a). First, the inputs are vertically shifted from the LBUF on top of each core. These inputs are all unique and they are pre-loaded to each PE for the input-stationary systolic dataflow. Compared to a single large systolic array, this saves half the input shifts due to the reduced core height. Next, both cores 0 and 2 pass the inputs shifted from the left LBUFs to core 1 and 3 for reuse in multiplication and accumulation operations (with the stationary inputs pre-loaded in core 1 and 3). At the same time, cores 0 and 1 pass their outputs (partial sums) directly to cores 2 and 3 for output reuse. Because the reuse of both vertically and horizontally shifted inputs is the same as the large core, FW has half the on-chip traffic compared to a naive independent four-core design.
FlexSA supports two systolic sub-array operations that use two pairs of cores independently. First, VSW (vertical sub-wave) forms two vertical systolic sub-arrays by paring the two cores in each column (cores 0 and 2 for one sub-array and cores 1 and 3 for the other as shown in Figure 8.b). This mode is designed for efficient processing of skinny GEMM tiles in parallel whose tile width is smaller than or equal to the width of one small core. VSW starts by pre-loading the same inputs to each of the two vertical sub-arrays. To reduce the cost of sending identical inputs from GBUF to the LBUFs of both sub-arrays, we construct switchable data paths between the LBUFs of cores 0/2 and 1/3 for local broadcast ❸. After pre-loading the stationary inputs, the other inputs are horizontally shifted to each sub-array. To provide different inputs to each sub-array in parallel, VSW uses the additional horizontal data paths ❶. VSW uses only half of the output buffers, as shown in Figure 8.b. Therefore, it is possible to interleave two VSWs that use the same stationary inputs but different horizontally shifted inputs. Overall, VSW improves PE utilization by executing two skinny GEMM tiles in parallel and also improves stationary input reuse by 2 through local broadcasting.
Second, HSW (horizontal sub-wave) constructs two horizontal systolic sub-arrays by paring the two cores in each row (cores 0/1 for one sub-array and cores 2/3 for the other as shown in Figure 8.c). HSW is designed for efficient mapping of fat GEMM tiles whose accumulation depth is smaller than or equal to the height of one small core. HSW first pre-loads the same stationary inputs to each horizontal sub-arrays. Then, the other inputs are shifted from the left LBUFs through both paired cores in each row. Similar to the local input sharing used in VSW, we construct a direct data path between the input buffers of cores 0/1 and cores 2/3 to avoid duplicated input transfers from the GBUF ❹. The outputs from cores 0 and 1 are directly stored and accumulated at the output buffers at the bottom of cores 2 and 3 ❷. Overall, HSW improves PE utilization by processing two fat GEMM tiles in parallel and doubles the reuse of horizontally shifted data compared to using small cores individually.
Lastly, FlexSA supports full independent core operation by providing unique inputs to each core as shown in Figure 8.d, which we call ISW (independent sub-wave). This mode helps maintain high PE utilization when both GEMM tile width and accumulation depth are small. ISW provides independent inputs horizontally to cores 1 and 3 using the additional data path ❶ and the outputs of core 1 and 2 are sent to and accumulated at the output buffers using the added vertical data path ❷. Compared to the independent core design, ISW exhibits lower input loading cost because FelxSA locally broadcasts the stationary inputs between cores. This saving is possible because the FlexSA compiler schedules waves sharing one of the two inputs in parallel rather than processing waves with all different inputs (we will discuss this in Section VI. However, since the input reuse of ISW is the lowest among all modes, other sub-array modes should be prioritized over ISW for cost-efficient execution.
V-B Area Overhead Estimation
FlexSA requires additional area for logic and data path wires and switches. We estimate area in 32 technology and we compare the overhead relative to the naive four-core design. Again, we conservatively estimate the area overhead of additional data paths assuming they do not overlap with logic. First, the addition of data path switches (1:2 MUXs) that select inputs and partial sums increase logic area by only 0.03. Second, FlexSA requires each PE at the top row of cores 2 and 3 to support a mixed-precision FMA (fused multiplier and adder) instead of just a 16-bit multiplier to accumulate the partial sums shifted from cores 0 and 1. This change increases the area by 0.32. Third, the repeaters to drive signals over a core add 0.25, where we use fanout of 32. The vertical wires connecting the outputs of cores 0 and 1 to the output buffers ❷ expand the width of the core by 0.09. However, the other wires do not affect die size because they are effectively canceled by the wiring overhead of connecting GBUFs and the LBUFs in the baseline four-core design.
Overall, FlexSA increases the die area over the naive four-core design by only 1%. This area estimate is conservative and placing the newly added vertical wires over PE array (as illustrated) can effectively hide the wiring area overhead. This is feasible because PE arrays use only a few low-level metal wires for local routing.
Design Scalability. It is possible to form a FlexSA unit using more than four cores. However, we present only the four-core design for three reasons. First, the performance benefit diminishes as we further split the cores to a larger number of smaller cores as shown in Figure 5. Second, grouping more than four cores incurs significantly higher area overhead. This area is for the larger number of wires, data switches, and repeaters required for constructing many independent sub-arrays Instead, we propose to construct multiple FlexSA units with four cores, which incurs no additional area overhead, making it scalable. We use this multi-FlexSA design to evaluate model pruning in Section VIII.
Vi FlexSA Compilation and GEMM Tiling
FlexSA mode selection is crucial for efficient GEMM processing. Modes should be selected to achieve the highest PE utilization with minimum on-chip data traffic. Mode selection is coupled with GEMM tiling because different modes are optimal for GEMM tiles with different shapes.
In this section, we introduce a compile-time GEMM tiling heuristics that tile a GEMM into systolic waves to best utilize FlexSA resources such that it achieves both high performance and energy efficiency. Here, a wave the GEMM execution granularity using the systolic array defined in Section II. The systolic waves are mapped to systolic array cores and executed using different FlexSA modes. Different modes require different micro-controls, such as data path selection, input shifting, output shifting, and partial sum accumulation. For efficient communication between software and the FlexSA micro-architecture, we introduce a set of instructions that define the micro-controls needed for each FlexSA mode and that handle data transfers between on-chip buffers.
Vi-a GEMM Tiling Heuristics
The proposed compile-time GEMM tiling heuristics choose waves that are executed on FlexSA with the highest PE utilization and in-core data reuse. In other words, systolic waves that use the FlexSA modes with greater input reuse are prioritized and the waves using the FlexSA modes with lower input reuse are chosen only when using them improves PE utilization (i.e., FWHSW=VSWISW).
GEMM Tiling Conditions for FW. The proposed heuristics tile a large GEMM into multiple waves to process them on the cores of FlexSA. The tiling factors of all GEMM dimensions (, , and in Figure 9.a) are chosen to match the size of a full FlexSA (all four cores of FlexSA) to maximize reuse by utilizing the FW mode. The sizes of and are equal to the width and height of a full FlexSA core, both of which are 128 in our baseline design. The size of is the size of the LBUF for non-stationary inputs (LBUFs on the left side of FlexSA in Figure 7) divided by the height of a full FlexSA core.
Because GEMM dimensions are not always a multiple of the ideal tile size, the execution of some tiles with FW would degrade utilization and performance. Such tiles (typically just the edge tiles of a large GEMM) are executed with the other FlexSA modes as shown in Figure 9 and discussed below.
GEMM Tiling Conditions for HSW. When the size of a systolic wave is small, using FW under-utilizes PEs and slows down the GEMM execution. Thus, when the size of is smaller than or equal to the height of one FlexSA core (a sub-core of FlexSA), the proposed heuristics execute the systolic wave using HSW as shown in Figure 9.b. By executing a single fat wave as two independent waves using the two horizontal sub-systolic arrays, HSW increases PE utilization by 2X.
GEMM Tiling Conditions for VSW. Tiles at the GEMM edges can have small block sizes in the dimension and executing the systolic waves of these skinny tiles using FW also under-utilizes PEs. Therefore, when the is smaller than or equal to the width of one FlexSA core, the heuristics execute the waves of the skinny GEMM tiles using VSW as shown in Figure 9.c. This improves PE utilization by executing the waves of two small GEMM tiles in parallel using the two vertical sub-systolic arrays. In particular, this skinny GEMM tile is executed using two VSW operations (VSW1 and VSW2 in Figure 9.c) that can be interleaved, accumulating their results using half of the output buffers. Because the two VSW operations share the stationary inputs, this achieves additional 2X stationary input reuse.
GEMM Tiling Conditions for ISW. When both and are smaller than the width and the height of one FlexSA core, respectively, the proposed heuristics execute the systolic waves using ISW. ISW executes a GEMM tile using four small independent waves, which operate in parallel to achieve high PE utilization (Figure 9.d). When a pair of VSWs precedes ISW like the case of Figure 9.c followed by Figure 9.d, the four small systolic waves executed by ISW accumulate their results with the partial sums pre-stored in the output buffers.
Vi-B ISA Support and Compilation for GEMM Processing
To execute the systolic waves using FlexSA, ISA support is necessary. First, an instruction to define the configurations of each FlexSA modes is needed. This instruction provides the type of FlexSA mode and the sizes of each wave’s , , and . This information is mapped to the micro-controls required to execute these waves such as data path selection, input shifting, output shifting, and accumulation. Second, vector load and store instructions are needed for efficient data transfers between the GBUF (global buffer) and LBUFs (local buffers). Using vectors reduces instruction count and instruction decoding BW, compared to using word-granularity instructions. The compiler generates memory access routines that load inputs to the LBUFs of cores and store the GEMM outputs to the GBUF or off-chip memory using these vector instructions.
Algorithm 1 shows how the FlexSA compiler processes a GEMM: generating instructions for data loading and FlexSA model selection. The compiler tiles the GEMM and schedules waves to process each GEMM tile. The type of each FlexSA mode is determined by the shape of the current systolic wave (IsWideWave and IsTallWave).
Before executing each wave (or waves in parallel), inputs for the wave(s) are loaded from the GBUF to LBUFs of FlexSA cores. For this, two vector load instructions (LdLBUF_V and LdLBUF_H) are used. These vector load instructions take address pointers for GBUF and LBUFs, and the size of the data to load. The LBUFs are double buffered to hide the access and transfer latency. Thus, the inputs to be used in the next systolic wave are pre-fetched while executing the current wave. Once stationary inputs are fully loaded at LBUFs, they are shifted to PEs using a ShiftV instruction. ShiftV takes a number of shifts and this is determined by the height of a wave. Using a separate instruction for stationary input shifting decouples it from the main systolic wave execution step and makes it parallel to loading non-stationary inputs to the LBUFs, removing unnecessary execution step serialization within a wave.
When both inputs are ready, an ExecGEMM instruction executes the target systolic wave using the selected FlexSA mode. ExecGEMM takes four inputs: the type of FlexSA mode and the sizes of the wave dimensions (, , and ). For HSW, VSW, and ISW, the sizes of these wave dimensions indicate those of each independent wave. When GEMM tile execution is complete after iterating over the dimension (processing all waves of a GEMM tile), the outputs accumulated at the OBUFs (output buffers) are stored to the GBUF using a StLBUF instruction.
Vii Evaluation Methodology and
Baseline Scheduling Policy
We develop an instruction-level architecture simulator to evaluate the performance and energy efficiency of FlexSA. We use three popular modern CNN models for evaluation: ResNet50, Inception v4 , and MobileNet v2 . ResNet50 is pruned during training using PruneTrain as the pruning mechanism with two different model-pruning strengths. Inception v4 is artificially pruned by applying the same pruning statistics of ResNet50. In case of MobileNet v2, we compare the training performance of the baseline model and its statically pruned version, which uses 75% of channels in all convolution layers as used in the original proposal . The model is trained for 90 epochs with a pruning interval of 10 epochs. We use a mini-batch size of 32 for ResNet50 and Inception v4 and a larger mini-batch of 128 for MobileNet v2 considering their off-chip memory capacity requirements. We use mixed-precision multiplication and accumulation  to execute the GEMMs of the convolution and FC layers.
In our evaluation, five different accelerator configurations are used, as summarized in Table I. The 1G1C configuration uses a single 128128 systolic array, 1G4G splits this large core into four 6464 cores, which share a single GBUF. The 4G4C configuration further splits the cores into 16 3232 cores, where we divide the cores and the GBUF into four groups with cores in each group sharing a GBUF. The 1G1F configuration has a single 128128 FlexSA with four 6464 cores, and 4G1F has four small FlexSAs, each with a dedicated GBUF. The systolic array cores operate with 0.7 Ghz clock frequency so all configurations have 23 TFLOPS. We use a GBUF of 10 MB as used in WaveCore  for all core configurations, and a single 270 GB/s HBM2 chip as the memory system . All local input and output buffers are sized to support input and output double buffering. The local input buffers holding the horizontally shifted inputs are two times larger than the input buffers holding stationary inputs to support the larger reuse of the pre-loaded stationary inputs.
DL models contain non-GEMM layers (e.g., feature normalization [45, 46], activation , and element-wise math layers), which tend to be bound by memory BW due to low arithmetic intensity. The execution time of these layers changes depending on accelerator design choices (off-chip memory BW and on-chip buffer design) and workload scheduling methods (multi-layer fusion , and layer fusion [49, 21]). To decouple the impact of these memory bound operations and concentrate on what we intend to improve with FlexSA, we mainly focus on convolution and FC layers that use matrix operations and discuss the impact of other layers.
GEMM Partitioning and Blocking. The convolution and FC layers have three GEMM execution phases: forward propagation and data gradient and weight gradient computations in back-propagation. The GEMMs in the forward propagation and data gradient computation are skinny: they have large GEMM height (M), which is the product of the mini-batch size and the feature size, and have small GEMM width (N), which is set by the number of output channels. Thus, when multiple core groups are used, we partition a GEMM across the M dimension with one partition per core group. On the other hand, the GEMMs for weight gradient computation have small GEMM dimensions in both height and width, but they have large accumulation dimension (K). In this case, we partition the GEMM across the accumulation dimension with one partition per group. Within each GEMM partition, we use 2-level GEMM blocking that holds the inputs of a multiple of GMEM tiles in the GBUF for reuse. Within each GEMM partition, each systolic wave is allocated to cores in a group in round-robin fashion. When partitioning GEMM across the M dimension, different core groups use the same inputs from the GEMM N dimension. These shared inputs between core groups are replicated to avoid expensive inter-group data transfers. We find that this method effectively distributes GEMM workloads to multiple cores and core groups.
Viii Evaluation Results
PE Utilization and Performance. Figure (a)a shows the average PE utilization of ResNet50, Inception v4, MobileNet v2 across training epochs using different core configurations. This experiment uses infinite (ideal) DRAM BW to isolate the impact on PE utilization to only the size mismatch between systolic waves and cores. The baseline 1G1C shows low average ideal PE utilization of 44% for the three CNNs. The PE utilization of Inception v4 and MobileNet v2 are lower than that of ResNet50 because many of their convolution layers have fewer than 128 channels and are smaller than the height and width of a core. Using one FlexSA (1G1F) improves the average PE utilization to 66% and by 49% compared to 1G1C because it processes the GEMM using tiles with higher PE occupancy so less internal PE utilization fragmentation. Using four FlexSA units (4G1F) further improves the PE utilization to 84% and by 89% compared to 1G1C showing diminishing return. Compared to 1G4C and 4G4C that use 4 and 16 small independent cores, 1G1F and 4G1F show only 0.1% less ideal PE utilization. Considering that the PE utilization of using independent small cores is the maximum that can be achieved with FlexSA. The result indicates that the FlexSA modes selected by the proposed heuristics achieve near-optimal PE utilization.
Figure (b)b shows the PE utilization and speedup using a single HBM2 for the DRAM system. Unlike using ideal memory BW, this reflects the performance impact from GEMM tiling, input blocking, and systolic wave scheduling. Therefore, for all configurations, PE utilization decreases compared to using ideal memory. Compared to using small independent cores (1G4C and 4G4C), both FlexSA configurations show smaller PE utilization drop contributing greater performance gains. This is because 1G4C and 4G4C always use small GEMM tiles and their performance suffers by increased DRAM BW peaks from executing many small independent systolic waves in parallel. FlexSA mitigates this overhead by using inter-core operating modes. Executing large waves using big cores increases arithmetic intensity per wave requiring low peak memory BW and small systolic waves are used only when using large waves decreases PE utilization. Overall, 1G1F and 4G1F achieve average pruning-while-training speedup of 37% and 47% compared to 1G1C and by 6% and 7% even compared to 1G4C and 4G4C, respectively. This is shown by red lines in Figure (b)b.
MobileNet v2 shows lower PE utilization compared to other CNNs because of its neural network architecture specifics. It uses pairs of depth-wise convolution layer and point-wise convolution layer, which have reduced input reuse. Thus, its performance becomes highly memory BW-bound with little on-chip reuse opportunity.
On-chip Traffic and Energy Efficiency. Other than improving PE utilization, FlexSA reduces on-chip traffic by improving in-core reuse. Figure 11 compares the on-chip traffic between the GBUF to LBUFs of convolution and FC layers of in different models, which are normalized to that of 1G1C. The naive many-core configurations (1G4C and 4G4C) increase the data traffic by 1.5 and 2.7, respectively, due to the reduced in-core reuse caused by using small independent systolic waves. On the other hand, the configurations using FlexSA show far lower data traffic compared to the naive many-core designs and similar traffic even compared to the design with larger cores. 1G1F reduces on-chip traffic by 36% compared to 1G4C, and by 2% even compared to 1G1C. This 2% traffic saving comes from reusing the stationary inputs and outputs between multiple systolic waves in processing VSW and ISW modes, which is not possible with the baseline core design. 4G1F also saves on average 43% GBUF traffic compared to 4G4C.
The reduced on-chip traffic from using FlexSA improves the energy efficiency of pruning and training. To show this, we evaluate the dynamic energy consumed per training iteration using different core configurations (Figure (a)a). Each bar indicates the breakdown of energy consumed by different accelerator operations. COMP indicates the energy consumed by mixed-precision multiply and accumulation operations of the FlexSA core. LBUF, GBUF, and DRAM indicate the energy spent on data transmission associated with different resources. OverCore indicates the over-core data transmission energy, which exists only in the configurations using FlexSA. The lines represent the energy increase compared to 1G1C. Both FlexSA configurations exhibit similar or even lower energy consumption than the baseline 1G1C. This high energy efficiency of FlexSA comes from using large systolic waves in most cases. The additional energy consumed by over-core data transmission is very small for all CNNs and pruning strengths. However, 1G4C and 4G4C exhibit 20% total energy increase for ResNet50 and Inception v4 compared to both FlexSA configurations due to reduced in-core reuse and replicated input loads between cores. The reason 4G4C shows similar energy compared to 1G4C though it requires higher traffic is that average global buffer access energy is lower with the distributed GBUFs. However, MobileNet v2 shows smaller energy increase with 1G4C and 4G4C shows even lower energy consumption than 1G1C. This is because DRAM access accounts for the dominant energy consumption of MobileNet v2 and GBUF energy takes relatively small portion with low on-chip reuse.
FlexSA Operating Modes Breakdown. Figure 13 shows the breakdown of FlexSA operating modes used in pruning with 1G1F (top row) and 4G1F (bottom row) configurations. Each pie graph averages the breakdown of using high and low pruning strengths. This shows how frequently large systolic waves are used to improve in-core reuse and save energy consumption. For 1G1F, the inter-systolic array operating modes (VSW, HSW, and FW) account for 94% for both ResNet50 and Inception v4 and 66% for MobileNet v2. For 4G4F, the ratio of using inter-systolic array operating modes increase to 99% for both ResNet50 and Inception v4 and to 85% for MombileNet v2. Especially, for ResNet50 and Inception v4, the least efficient ISW accounts for only 6% and 1% for 1G1F and 4G1F. MobileNet v2 shows a bit greater ISW usage because it uses tensors with small dimensions. This result indicates that the high-reuse inter-core operations of FlexSA are used frequently and still achieve very high utilization.
Performance and Energy Impact of Other Layers. We evaluate the impact of other layers without layer fusion. This is a conservative assumption given many of memory-bound math layers can be executed while executing GEMMs. We use SIMD array with 500 GFLOPS to execute the data-parallel operations, which is the 1/50 of the throughput of the systolic arrays. Based on our evaluation, 1G1F and 4G1F improves end-to-end training performance of all three CNNs by 24% and 29%, respectively, compared to 1G1C. This is also 3% performance improvement compared to the simple many-small-core designs. This performance gain will increase when aggressive layer fusion is considered . The FlexSA configurations also save overall dynamic energy in training by 10% compared to the many-small-core designs.
In this paper, we tackle the problems in training (partially) pruned CNN models using a high-throughput accelerator with systolic arrays. The GEMMs of structurally pruned CNN models have reduced dimensions, which decreases PE utilization when processed on large systolic arrays. Although splitting a large systolic array into multiple small arrays improves PE utilization, it decreases in-core data reuse, increasing on-chip traffic and energy consumption.
To improve the PE utilization without affecting reuse, we present FlexSA, a flexible systolic array architecture that dynamically reconfigures its structure to efficiently process systolic waves with different sizes and shapes. FlexSA consists of four sub-systolic array cores and designing it adds only 1% area compared to a naive four-core design. FlexSA supports four different systolic array operating modes and each is designed to efficiently process systolic waves with different shapes, forming different inter-core systolic dataflows. Our FlexSA compiler supports optimal utilization of the underlying FlexSA resources using an efficient mode selection heuristic and custom instructions. Overall, FlexSA improves PE utilization of pruning while training CNN models by 37% compared to using a single large core and increase on-chip reuse by 1.7X compared to small-many-core designs, saving dynamic energy by 28%.
-  S. Han, H. Mao, and W. J. Dally, “Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding,” arXiv preprint arXiv:1510.00149, 2015.
-  S. Han, J. Pool, J. Tran, and W. Dally, “Learning both weights and connections for efficient neural network,” in Advances in neural information processing systems, 2015, pp. 1135–1143.
-  H. Li, A. Kadav, I. Durdanovic, H. Samet, and H. P. Graf, “Pruning filters for efficient convnets,” arXiv preprint arXiv:1608.08710, 2016.
-  P. Molchanov, S. Tyree, T. Karras, T. Aila, and J. Kautz, “Pruning convolutional neural networks for resource efficient transfer learning,” CoRR, abs/1611.06440, 2016.
Y. He, X. Zhang, and J. Sun, “Channel pruning for accelerating very deep
neural networks,” in
International Conference on Computer Vision (ICCV), vol. 2, no. 6, 2017.
-  H. Hu, R. Peng, Y.-W. Tai, and C.-K. Tang, “Network trimming: A data-driven neuron pruning approach towards efficient deep architectures,” arXiv preprint arXiv:1607.03250, 2016.
-  Y. He, J. Lin, Z. Liu, H. Wang, L.-J. Li, and S. Han, “Amc: Automl for model compression and acceleration on mobile devices,” in Proceedings of the European Conference on Computer Vision (ECCV), 2018, pp. 784–800.
-  S. Lym, E. Choukse, S. Zangeneh, W. Wen, S. Sanghavi, and M. Erez, “Prunetrain: fast neural network training by dynamic sparse model reconfiguration,” in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2019, pp. 1–13.
-  J. M. Alvarez and M. Salzmann, “Compression-aware training of deep networks,” in Advances in Neural Information Processing Systems, 2017, pp. 856–867.
-  N. Gamboa, K. Kudrolli, A. Dhoot, and A. Pedram, “Campfire: Compressible, regularization-free, structured sparse training for hardware accelerators,” arXiv preprint arXiv:2001.03253, 2020.
-  W. Wen, C. Wu, Y. Wang, Y. Chen, and H. Li, “Learning structured sparsity in deep neural networks,” in Advances in Neural Information Processing Systems 29, D. D. Lee, M. Sugiyama, U. V. Luxburg, I. Guyon, and R. Garnett, Eds. Curran Associates, Inc., 2016, pp. 2074–2082.
-  N. P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers et al., “In-datacenter performance analysis of a tensor processing unit,” in Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017, pp. 1–12.
-  S. Cyphers, A. K. Bansal, A. Bhiwandiwalla, J. Bobba, M. Brookhart, A. Chakraborty, W. Constable, C. Convey, L. Cook, O. Kanawi et al., “Intel ngraph: An intermediate representation, compiler, and executor for deep learning,” arXiv preprint arXiv:1801.08058, 2018.
-  K. Hao, ““tesla says its new self-driving chip will help make its cars autonomous,” MIT Technology Review, 2019.
-  S. Gray, A. Radford, and D. P. Kingma, “Gpu kernels for block-sparse weights,” arXiv preprint arXiv:1711.09224, vol. 3, 2017.
K. He, X. Zhang, S. Ren, and J. Sun, “Deep residual learning for image
Proceedings of the IEEE conference on computer vision and pattern recognition, 2016, pp. 770–778.
C. Szegedy, S. Ioffe, V. Vanhoucke, and A. A. Alemi, “Inception-v4, inception-resnet and the impact of residual connections on learning,” in
Thirty-first AAAI conference on artificial intelligence, 2017.
-  J. Devlin, M.-W. Chang, K. Lee, and K. Toutanova, “Bert: Pre-training of deep bidirectional transformers for language understanding,” arXiv preprint arXiv:1810.04805, 2018.
-  A. Vaswani, N. Shazeer, N. Parmar, J. Uszkoreit, L. Jones, A. N. Gomez, Ł. Kaiser, and I. Polosukhin, “Attention is all you need,” in Advances in neural information processing systems, 2017, pp. 5998–6008.
-  S. Lym, D. Lee, M. O’Connor, N. Chatterjee, and M. Erez, “Delta: Gpu performance model for deep learning applications with in-depth memory system traffic analysis,” in 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 2019, pp. 293–303.
-  S. Lym, A. Behroozi, W. Wen, G. Li, Y. Kwon, and M. Erez, “Mini-batch serialization: Cnn training with inter-layer data reuse,” arXiv preprint arXiv:1810.00307, 2018.
-  NVIDIA, Deep learning SDK documentation, 2019. [Online]. Available: https://docs.nvidia.com/deeplearning/sdk/dl-performance-guide/index.html
-  N. S. Keskar, D. Mudigere, J. Nocedal, M. Smelyanskiy, and P. T. P. Tang, “On large-batch training for deep learning: Generalization gap and sharp minima,” arXiv preprint arXiv:1609.04836, 2016.
-  B. Neyshabur, S. Bhojanapalli, D. McAllester, and N. Srebro, “Exploring generalization in deep learning,” in Advances in Neural Information Processing Systems, 2017, pp. 5947–5956.
-  S. Han, J. Kang, H. Mao, Y. Hu, X. Li, Y. Li, D. Xie, H. Luo, S. Yao, Y. Wang et al., “Ese: Efficient speech recognition engine with sparse lstm on fpga,” in Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2017, pp. 75–84.
-  J. Yu, A. Lukefahr, D. Palframan, G. Dasika, R. Das, and S. Mahlke, “Scalpel: Customizing dnn pruning to the underlying hardware parallelism,” in ACM SIGARCH Computer Architecture News, vol. 45, no. 2. ACM, 2017, pp. 548–560.
-  S. Anwar, K. Hwang, and W. Sung, “Structured pruning of deep convolutional neural networks,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 3, p. 32, 2017.
-  A. G. Howard, M. Zhu, B. Chen, D. Kalenichenko, W. Wang, T. Weyand, M. Andreetto, and H. Adam, “Mobilenets: Efficient convolutional neural networks for mobile vision applications,” arXiv preprint arXiv:1704.04861, 2017.
-  Z. Zhuang, M. Tan, B. Zhuang, J. Liu, Y. Guo, Q. Wu, J. Huang, and J. Zhu, “Discrimination-aware channel pruning for deep neural networks,” in Advances in Neural Information Processing Systems, 2018, pp. 875–886.
-  X. Gao, Y. Zhao, Ł. Dudziak, R. Mullins, and C.-z. Xu, “Dynamic channel pruning: Feature boosting and suppression,” arXiv preprint arXiv:1810.05331, 2018.
-  H.-T. Kung, “Why systolic architectures?” Computer, no. 1, pp. 37–46, 1982.
-  A. Samajdar, Y. Zhu, P. Whatmough, M. Mattina, and T. Krishna, “Scale-sim: Systolic cnn accelerator simulator,” arXiv preprint arXiv:1811.02883, 2018.
A. Krizhevsky, I. Sutskever, and G. E. Hinton, “Imagenet classification with deep convolutional neural networks,” inAdvances in neural information processing systems, 2012, pp. 1097–1105.
-  K. He, G. Gkioxari, P. Dollár, and R. Girshick, “Mask r-cnn,” in Proceedings of the IEEE international conference on computer vision, 2017, pp. 2961–2969.
-  J. Redmon, S. Divvala, R. Girshick, and A. Farhadi, “You only look once: Unified, real-time object detection,” in Proceedings of the IEEE conference on computer vision and pattern recognition, 2016, pp. 779–788.
-  Google, “Google tpu system architecture,” White paper. [Online]. Available: https://cloud.google.com/tpu/docs/system-architecture
-  E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym, “Nvidia tesla: A unified graphics and computing architecture,” IEEE micro, vol. 28, no. 2, pp. 39–55, 2008.
-  M. Gao, J. Pu, X. Yang, M. Horowitz, and C. Kozyrakis, “Tetris: Scalable and efficient neural network acceleration with 3d memory,” ACM SIGOPS Operating Systems Review, vol. 51, no. 2, pp. 751–764, 2017.
-  K. Chen, S. Li, N. Muralimanohar, J. H. Ahn, J. B. Brockman, and N. P. Jouppi, “Cacti-3dd: Architecture-level modeling for 3d die-stacked dram main memory,” in Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 2012, pp. 33–38.
-  H. Zhang, H. J. Lee, and S.-B. Ko, “Efficient fixed/floating-point merged mixed-precision multiply-accumulate unit for deep learning processors,” in 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018, pp. 1–5.
Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang, L. Li, T. Chen, Z. Xu,
N. Sun et al.
, “Dadiannao: A machine-learning supercomputer,” inProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2014, pp. 609–622.
-  M. Sandler, A. Howard, M. Zhu, A. Zhmoginov, and L.-C. Chen, “Mobilenetv2: Inverted residuals and linear bottlenecks,” in 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition. IEEE, 2018, pp. 4510–4520.
-  P. Micikevicius, S. Narang, J. Alben, G. Diamos, E. Elsen, D. Garcia, B. Ginsburg, M. Houston, O. Kuchaiev, G. Venkatesh et al., “Mixed precision training,” arXiv preprint arXiv:1710.03740, 2017.
-  High Bandwidth Memory (HBM) DRAM, JESD235A, Joint Electron Device Engineering Council, Jan. 2016.
-  S. Ioffe and C. Szegedy, “Batch normalization: Accelerating deep network training by reducing internal covariate shift,” arXiv preprint arXiv:1502.03167, 2015.
-  Y. Wu and K. He, “Group normalization,” in Proceedings of the European Conference on Computer Vision (ECCV), 2018, pp. 3–19.
-  T. Chen, T. Moreau, Z. Jiang, L. Zheng, E. Yan, H. Shen, M. Cowan, L. Wang, Y. Hu, L. Ceze et al., “TVM: An automated end-to-end optimizing compiler for deep learning,” in 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), 2018, pp. 578–594.
-  M. Alwani, H. Chen, M. Ferdman, and P. Milder, “Fused-layer cnn accelerators,” in 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016, pp. 1–12.