Extending High-Level Synthesis for Task-Parallel Programs

09/23/2020
by   Yuze Chi, et al.
0

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA accelerators. In this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22 51 correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2xand 6.8x, respectively.

READ FULL TEXT

page 4

page 8

page 9

research
05/18/2023

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation

Recent years have witnessed the growing popularity of domain-specific ac...
research
08/27/2015

Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay

Offloading compute intensive nested loops to execute on FPGA accelerator...
research
09/30/2020

AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators

Adopting FPGA as an accelerator in datacenters is becoming mainstream fo...
research
03/05/2019

Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design

High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamili...
research
11/17/2021

Early DSE and Automatic Generation of Coarse Grained Merged Accelerators

Post-Moore's law area-constrained systems rely on accelerators to delive...
research
05/08/2017

A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development

Productivity issues such as lengthy compilation and limited code reuse h...
research
04/07/2022

Towards Comparing Performance of Algorithms in Hardware and Software

In this paper, we report on a preliminary investigation of the potential...

Please sign up or login with your details

Forgot password? Click here to reset