1. Introduction
With sustained advancement in IC fabrication technology, stringent design rules are evolving by exponentially large numbers. Straightforward routing solutions from a HPWL aware placement solution may not yield an acceptable physical design closure due to too many routing violations in subsequent global routing. If these violations are not resolved by the subsequent detailed routing or by an iterative global and detailed routing, the placement (or floorplanning or even logic restructuring) of the design should be redone. In practice, several iterations in block placement (and floorplanning) are required for complex designs containing multimillion gates in order to attain a feasible routing solution (see Fig. 2 (a)). Therefore, it has been a mandate to consider different global routing metrics such as routability, wirelength, congestion (Chang et al., 2003; Liu et al., 2013; Lin and Chu, 2014) and even timing (Sherwani, 1995) as the prime objectives in a placement problem. Some placement engines, however, integrated faster global routing solutions for iterative improvement of the placement solution (He et al., 2013; Pan and Chu, 2006, 2007; Viswanathan and Chu, 2005; Viswanathan et al., 2006). For fewer design iterations before successful routing closure, integrated global/detailed routing methods were also explored (Zhang and Chu, 2012).
Modern VDSM fabrication processes, such as and below, continue to allow more routing layers with varying metal width/pitch for successful routing completion. A routing solution with excessive via count not only causes design for reliability issues due to random via failures (Chen and Chang, 2009), but also impacts the circuit performance due to increased resistance along the routing paths with more vias. Double via insertion during postrouting layout optimization or identifying a viafailure aware routing (Chen and Chang, 2009) as depicted in Fig. 1 or even redundant via aware ECO routing during mask optimization (Chien and Wang, 2014) for increased reliability and yield of the fabricated design are some of the known approaches to minimize these failures. Moreover, vias consume substantial routing area and pose as additional routing blockages in the routing regions impacting routability of the design. Therefore, via minimization (Sherwani, 1995) is a critical problem to handle in physical design flow. There are two approaches: (a) unconstrained via minimization (UVM), and (b) constrained via minimization (CVM). While UVM identifies a routing path of a net with minimal number of vias along it for a given number of routing (metal) layers, CVM approaches aims to minimize the number of vias while keeping the routing topology unchanged. This routing topololy is obatined by planar routing solution during early phases of global routing. Although, both are known to be NPhard problems, UVM is much harder than CVM (Sherwani, 1995; Hsu, 1983). Existing global routers (Cho et al., 2009; Pan and Chu, 2006; Roy and Markov, 2008; Xu et al., 2009), except a few like (Cao et al., 2008; Lu and Sham, 2013; MarekSadowska, 1984; Zhang et al., 2008), used CVM based layer assignment approaches on a planar routing solution for reducing via count as well as mitigating congestion (Lee and Wang, 2008).
Recently, an early global routing (EGR) method STAIRoute (Kar et al., 2013) was proposed for early routability assessment of a floorplanned layout, facilitated by a monotone staircase cut based recursive floorplan bipartitioning framework (Kar et al., 2012; Majumder et al., 2004, 2007). These bipartitioners work on any floorplan irrespective of their sliceability. As (Guruswamy and Wong, 1988; SurKolay and Bhattacharya, 1991) pointed out, the monotone staircase routing framework ensures an well defined routing order of the nets, based on the net cut information available with the nodes in the bipartitioning hierachy (Kar et al., 2012; Majumder et al., 2004, 2007). As highlighted in Fig. 2 (b), STAIRoute works in two stages: (a) enumerating the monotone staircase routing regions in a floorplan by recursive bipartitioning using monotone staircase cuts (Kar et al., 2012; Majumder et al., 2004, 2007), and (b) proposing an early global routing model for routing these nets through a number of metal layers, using these bipartitioning results.
The existing bipartitioning methods using monotone staircase cuts (Dasgupta et al., 2002; Kar et al., 2012; Majumder et al., 2004, 2007) considered only two objectives: (i) the area (number) of the blocks in each bipartition to be maximized, and (ii) the number of nets cut by a bipartition be minimized. While the former objective is related to the height of the bipartition hierarchy (also known as MSC tree (Kar et al., 2012)), minimizing the number of nets being cut has several advantages like: (a) distributing the routing paths of the nets uniformly across the entire layout, (b) reducing routing violations due to congestion hotspots (congestion ), (c) achieving uniform wire distribution across the layout for minimal variation due to chemical mechanical polishing (CMP) process, and (d) minimizing crosstalk effect due to long (global) nets running through the longer staircases, specially those nets corresponding to the upper nodes in the bipartition tree. In global routing, routing path of a net using multibend monotone pattern routing and its variants L/Z patterns (Cao et al., 2008; Kastner et al., 2002) is confined within the net bounding boxes. Therefore, identification of a minimal bend monotone patterns can potentially yield fewer via counts, while L/Z patterns use minimum of one/two vias respectively for minimum layer change.
In this work, we propose a new recursive floorplan bipartitioning framework, for identifying minimal bend monotone staircase routing regions in a floorplan, in order to use fewer vias during early global routing of the nets in the floorplan. The key contributions of this paper are:

define a new objective of bend minimization in the existing multiobjective floorplan bipartitioning problem;

propose a greedy method for identifying minimal bend monotone staircase routing regions for early global routing with smaller via count (this is an early approach for unconstrained via minimization (UVM); and

introduce a randomized neighbor search technique and staircase wave front propagation approach for exploring a larger solution space of potentially optimal minimal bend monotone staircase regions in a floorplan.
The organization of this paper is as follows: in Section 2, we discuss the background on monotone staircase routing region definition in a floorplan. The proposed floorplan bipartitioning method, for identifying a set of monotone staircases with minimal number of bends for the entire floorplan, is presented in Section 3. Section 4 discusses the basis for an extension of this greedy bipartitioning method and illustrates a new randomized neighbor search technique and the corresponding staircase wavefront propagation approach. Experimental results and relevant discussions are covered in Section 5, followed by the summary of this work in Section 6.
2. Background on Monotone Staircase Cuts
Before discussing the proposed recursive floorplan bipartitioning method, we revisit the formulation of an unweighted directed graph , namely block adjacency graph (BAG) (Kar et al., 2012; Majumder et al., 2004), used to define the adjacency relation of a set of blocks in a given floorplan . The graph is defined as follows: the vertex set = { corresponds to block } and the edge set where = {(,) block is on the left of (above) an adjacent block in }. The vertices corresponding to the topleft and the bottomright corner blocks are designated as the source and the sink vertices respectively, with zero indegree and outdegree respectively. This definition yields a monotonically increasing staircase (MIS) (see Fig. 3 (a)).
The definition of BAG for obtaining a monotonically decreasing staircase (MDS) is as follows: edge ={() for a pair of adjacent blocks () such that is to the left of (below) }. The source and sink vertices are identified as the vertices pertaining to the bottomleft and topright corner blocks respectively. This scenario is captured in Fig. 3 (b) along with the MDS cut . In the rest of the paper we refer an MIS/MDS cut as a mscut unless stated explicitly. It is to be noted that, unlike in (Majumder et al., 2004, 2007), this graph based framework does not consider any netlist information while constructing BAG for faster bipartitioning results. The netlist information is solely used to identify the cut nets and the uncut nets that fall on either side of the bipartition. These uncut nets and the respective parts of the cut nets with atleast two pins in each part. In this method, net cut information in each level of the bipartition hierarchy is a measure of the optimality of each mscut obtained, and is referred to as mincut balanced floorplan bipartitioning (Majumder et al., 2004, 2007).
In order to ensure each cut in BAG is an mscut, we refer to the following lemma given in (Majumder et al., 2004), commonly known as monotone staircase property.
Lemma 2.1 ().
If is an arc in , then there exists at least one monotone staircase in the floorplan such that the blocks and appear in the left and right partitions respectively, and there exists no staircase with in the right partition and in the left partition.
Proof.
In (Majumder et al., 2004). ∎
In Fig. 4, we illustrate the working of Lemma 2.1 for an MIS cut, which is equally applicable for an MDS cut. It shows that all the cut edges in the BAG are forward edges, i.e., directed from the left partition containing the source vertex towards the right partition containing the sink vertex yielding a valid monotone staircase cut. However, in Fig. 4 (b), the highlighted edge (,) in the BAG is directed from the right partition to the left partition. This cut leads to a nonmonotone staircase cut. From this illustration and Lemma 2.1, we observe that it requires at least one back edge directed from the right to left partition to generate a nonmonotone staircase cut.
Corollary 2.2 ().
Given a BAG formulated for obtaining a MIS (MDS) cut, any cut which has at least one back edge results in a nonmonotone staircase cut.
In order to study the advantage of early global routing using monotone staircase patterns over nonmonotone staircases, we consider the example in Fig. 5 for two different routing instances of a two pin net having terminal pins (, ). Wirelength for the monotone routing path is equal to half of the bounding box length of the net, i.e., half perimeter wirelength (HPWL), while that of the nonmonotone path yields extra wirelength beyond HPWL. This eventually consumes more routing area and hence increases the congestion in the routing regions, impacting the routability of the nets. A nonmonotone pattern may also require more number of vias depending the number of bends in it. On the other hand, a suitably chosen monotone staircase pattern with fewer bends in it may yield fewer via counts. Therefore, pattern routing using nonmonotone staircases is not beneficial for identifying a shortest routing path, as well as fewer via counts. Nevertheless, nonmonotone routing (Zhang et al., 2008) or maze routing (Lee, 1961; Sherwani, 1995) can be effective when monotone or L/Z (Kastner et al., 2002; Cao et al., 2008) patterns can not be used due to heavy congestion and more routing blockages due to already routed nets within the bounding box of a net. This leads to a detoured routing path with increased wirelength and possibly higher via count, identified using nonmonotone or maze routing.
Our study also shows that a very large number of monotone routing paths with varying number of bends are possible within the bounding box of a net, L/Z patterns being a subset of all those possible patterns with only one/two via overhead. An optimal monotone pattern is the one which takes minimal number of (bends) vias to complete the routing between a pair of pins through a set of metal layers, thus motivating this work. In this paper, the proposed recursive bipartitioning framework identifies a set of optimal monotone staircases with minimal number of bends in a given floorplan, for early global routing of the nets with minimal wirelength and via count. In this paper, we used only STAIRoute as the early global routing tool, by preferred directional routing in different metal layers.
3. Monotone Staircase Bipartitioning with Minimal Bends
In this section, we discuss the proposed recursive floorplan bipartitioning method in order to identify a set of minimal bend monotone staircase routing regions in a floorplan, for obtaining the shortest routing paths of a set of nets in floorplan, by an early global routing framework such as STAIRoute (Kar et al., 2013). Before that, we study the impact of a number of bends in a monotone staircase routing region on the number of vias when a net is routed through it, using reserved layer model for layer assignment of the net segments in different routing layers. In this routing model, horizontal and vertical segments of a net are routed through designated metal layers, say and respectively (see Fig. 5). This requires interlayer metal interconnects, called vias, to establish electrical connections between the wire segments of a net running in different layers. For the sake of simplicity, we assume routing with two routing layers (), although it can be extended to any number of permissible layers in the fabrication processes.
We consider two different routing instances between the terminal points (pins) and of a net segment as depicted in Fig. 6. These routes, denoted as and respectively, use different monotone staircase paths with different bend counts. While routing path uses five vias, requires only three vias. From this example, we infer that a monotone staircase with fewer bends can potentially reduce the number of vias when a net is routed through it using different metal layers and hence serves as the motivation of this work.
The problem definition in this work is augmented over the existing bipartitioning methods such (Dasgupta et al., 2002; Kar et al., 2012; Majumder et al., 2004, 2007), considering a new objective of bend minimization. We enlist the objectives of this new multiobjective optimization problem as below:

balance ratio = min(,)/max(,) be maximized

the number of cut nets () be minimized, and

the number of bends () in the monotone staircase be minimized
where , the area of the left (right) partition and
denotes the set of blocks in the left (right) partition. The number balanced bipartition problem can be seen as a restricted version of the area balanced bipartitioning problem when the area of each block is almost equal, i.e., having negligible variance in block area such that they can be normalized to unity. In this case,
is defined as min(,)/max(,), where () denotes the number of blocks in the left (right) partition.A linear combination function of these objectives, with a pair of tradeoff parameters (, ), is defined as below:
(1) 
where is the maximum possible number of bends if the constituent rectilinear segments in the corresponding monotone staircase had alternating (vertical or horizontal) orientation. It is computed as one fewer than the number of segments in it. Notably, Eqn. 1 is similar to that defined in (Kar et al., 2012) when . Careful selection of (, ) pair may yield an optimal balance among these objectives, not necessarily a global optimum. Since the area balanced bipartitioning is an NPhard problem (Majumder et al., 2007), the optimum balance among these objectives is hard to obtain in polynomial time. Instead, for a given (, ) pair, an optimal monotone staircase with maximum is chosen out of those with values in the sequence of bipartitions of a floorplan of blocks (Kar et al., 2012) (see Fig. 7), at a given bipartition hierarchy. In Section 5, we study the bipartitioning results with a range of (, ) values on a set of floorplan benchmark circuits.
Now we refer to Fig. 7 for the working of this bipartitioning framework while maximizing the area in each partition and assessing the corresponding bends in the resulting monotone staircase. In this study, we do not consider minimal net cut for the sake of simplicity and restrict only to area balance and minimal bend count. The bipartition instance in Fig. 7 (a) and (h) gives minimum number of bends (), but with poor area balance. The area balance between the partitions keeps on improving through the instances depicted in Fig. 7 (b)(e) with varying number of bends, while it declines for instances shown in Fig. 7 (f)(h). The best possible area balance may be attained in case of the bipartition in Fig. 7 (e), but yields the worst bend count () among all others. Therefore, a suitable tradeoff between area balance and bend count has to be made based on (, ) values. The bipartition instance with in Fig. 7 (d) appears to be a good choice among all the other instances. The following lemma gives a measure of the number of bends in a monotone staircase.
Lemma 3.1 ().
Given a floorplan with blocks, the number of bends in a monotone staircase routing region is .
Proof.
The number of bends in a monotone staircase can be at most one fewer than the number of cut edges in BAG due to alternate orientation of the contiguous cut edges. Since is a planar graph (Kar et al., 2012; Majumder et al., 2004) and is , the number of cut edges (a subset of ) that constitutes a monotone staircase is also . ∎
3.1. The Algorithm: BFS based Greedy Approach
The pseudocode for the proposed monotone staircase bipartitioning method with minimal bends, namely MSCut_Bend_BFS, is presented in Algorithm 1. The inputs to this method are the BAG obtained from a given floorplan of a set of blocks , a set of nets , the tradeoff parameters (, ) such that . The balance type dictates either an area or a number balanced bipartitioning (Majumder et al., 2004, 2007). Unlike the previous works, we focus on area balanced bipartitioning only, since number balanced mode is a special case of it. The key differences between MSCut_Bend_BFS and the bipartitioning method in (Kar et al., 2012) are: (i) bend minimization considered as an additional objective, and (ii) no restriction on the convergence within userdefined area bounds. In rare floorplan instances, these area bounds in (Kar et al., 2012) may lead to exploration of a sequence of monotone staircases. On contrary, our method is able to explore a sequence of staircases without any such constraints on any floorplan of blocks.
The recursive procedure for obtaining a set of minimal bend monotone staircases for the entire floorplan is presented in Algorithm 2, by recursively calling MSCut_Bend_BFS with a set of required inputs. Here, dictate the output staircase type, either an MIS or MDS (see Fig. 3). In this procedure, the root node of the bipartition hierarchy starts with a particular type e.g. MIS, followed by alternating types in the subsequent levels of the hierarchy. An example of a bipartition (MSC) tree in Fig. 8 illustrates a set of optimal monotone staircases (MIS/MDS) with minimal bends are overlaid on an input floorplan of blocks.
Theorem 3.2 ().
Given a floorplan with blocks and nets, Hier_MSCut_Bend takes time to generate a hierarchy of minimal bend monotone staircases in it.
Proof.
Since the block adjacency graph of a given floorplan instance for blocks is a planar graph, its construction takes time. By Lemma 3.1, each while loop in Algoritth 1 (MSCut_Bend_BFS) takes for identifying bends and for net bipartition. Thus, at any recursion level , each call to MSCut_Bend_BFS takes , i.e., . Since, MSCut_Bend_BFS yields a (nearly) balanced bipartition of the (sub)floorplans at each recursion, the number of levels in the bipartition hierarchy (called MSC tree (Kar et al., 2012)) is . Therefore, for the entire bipartition hierarchy of levels, the recursive procedure Hier_MSCut_Bend takes time to identify a set of minimal bend monotone staircases for the entire floorplan . ∎
In Section 5, we provide a few experimental results to show that the bipartition hierarchy, i.e., MSC tree has height for any floorplan instance of a circuit containing blocks with any area distribution.
4. A New Randomized Neighbor Search Approach
Given floorplan for a set of blocks, the number of all possible monotone staircases in is exponentially large. Hence, the problem of finding the optimum monotone staircase is known to be NPHard (Dasgupta et al., 2002; Majumder et al., 2007). As discussed in Section 3, an (near) optimal solution of monotone staircase bipartition implies a suitable tradeoff between the constituent objectives: (a) maximizing the area of each bipartition, (b) minimizing the number of bends in the corresponding monotone staircase, and (c) the number of cut nets by this bipartition. Since the area balanced bipartitioning is an NPHard problem (Majumder et al., 2007)
, no polynomial time algorithm exists. Hence, several greedy heuristic approaches have been proposed in
(Dasgupta et al., 2002; Kar et al., 2012; Majumder et al., 2004, 2007) and in Section 3. In all cases, a monotone staircase cut with the maximum value pertaining to a given tradeoff among the objectives is considered as an optimal bipartition. As stated in Section 3, we pick an (nearly) optimal monotone staircase among a sequence of monotone staircases for a given () pair. Intuitively, different () pairs may potentially yield different optimal solution(s) and even a different sequence.Given a set of blocks for a given floorplan , a monotone staircase bipartition (, ) represents a proper subset of . In other words, the blocks in the left partition (hence the right partition = ) constitute a proper subset of , while obeying the monotone staircase property (refer to Lemma 2.1 (Majumder et al., 2004)). Thus, (, ) represents a valid monotone staircase cut on the block adjacencyy graph (BAG) for . In summary, the set of all possible monotone staircases in is a subset of power set of (). Notably, is a partially ordered set by inclusion operation on all the monotone staircases in that can be identified in exponential time. A staircase covers a set of one or more staircases if can be obtained from . Based on this, we construct the corresponding hasse diagram (has, [n. d.]) pertaining to . An example hasse diagram for a floorplan of = (and ) is illustrated in Fig. 9.
In Section 3 and also in (Kar et al., 2012), we studied that a sequence of monotone staircases can be identified greedily at any level of bipartition hierarchy by the respective bipartitioning methods. An optimal solution is identified from this sequence based on a given tradeoff (). There is a scope of obtaining an improved solution if more than staircases can be explored, with proportionally higher runtime overhead. In this section, we present a new technique for exploring the neighbors of a block (vertex) in the BAG for a potentially better optimal monotone staircase (obeying Lemma 2.1 in terms of the objectives considered. We study how selection of a neighbor is done based on random indexing of the neighbors of vertex in . Alike the BFS based method (see Algorithm 1), the proposed bipartitioning method also adopts BFS on . However, this method can more aptly resemble with an wavefront propagation in Ether. This may lead to different sequences of (not necessarily disjoint) monotone staircase cuts on the BAG. In Fig. 9 (b), an example of these sequences are highlighted by different paths, one with black and other by blue color, from START to STOP node in the hasse diagram. In this diagram, each node represent a distinct monotone staircase and edges represent their possible transition to another distinct monotone staircase. In other words, these edges represent the inclusion operation. While the directed search method in Section 3 identifies only one sequence marked by the bold black line in Fig. 9 (b), the randomized method under discussion identifies different sequences during different trials of the proposed randomized neiighbor search technique. Notably, the number of sequences obtained by the random method can be more than one, but are not necessarily maximally disjoint. It is also evident that the length of such a path (START STOP) is always as stated in Lemma of (Kar et al., 2012). However, the number of such paths grow exponentially with and the sequences (hence the Hasse diagram) also differ due to different floorplan topology for the same set of blocks . A comparative study of staircase wavefront propagation using greedy and randomized neighbor search technique is presented in Appendix 7.1.
In Fig. 9 (b), we consider an example of two different sequences of monotone staircases marked by the blue and black lines, out of exponentially large number of possible sequences between START and STOP nodes. Here START and STOP nodes denote trivial monotone staircases containing only one block in the left (right) partition. If one path does not contain an optimal monotone staircase, another path may be explored in a hope to identify an optimal one. Since area balanced monotone staircase bipartitioning is a NPhard problem, there is no method that verifies such a scenario, unless we apply the brute force method to explore all possible sequences. However, a random transition from one node to another may lead to traversing a new path either completely or partially. Careful study of Fig. 9 (b) shows that randomization at the suitable node, say in this case , choosing the block randomly instead of (by greedy approach) may guide to a different sequence leading to a potentially optimal solution , for a given (, ) pair. In summary, several such randomized selections (while traversing from START STOP) may yield an optimal solution or a scope of obtaining a better solution than the previously found optimal solution. A number of such trials may be exercised in order to explore partially/completely different sequences and thus obtain a potentially better solution. However, in order to contain the run time within the same bound as in Section 3, a large number of such trials can not be afforded. Instead, we restrict the number of trials to a reasonably small number and use random seeds for each trial. After all such trials, an optimal monotone staircase is identified as the one, with maximum value, among all the staircases explored along different paths in START STOP.
In the proposed randomized neigbor search method (Kar et al., 2015), the underlying process of randomly indexing the neighbors of a vertex of brings in the difference with the greedy methods (Kar et al., 2012, 2014). Unlike greedy indexing approach, from left to right used in (Kar et al., 2012) and also in Section 3 (see Fig. 10 (a)), a neighbor of with outdegree is indexed with randomly chosen number (see Fig. 10 (b)). As in (Kar et al., 2012) (also Section 3), identifying a set of monotone staircases while exploring all adjacent vertices of takes time for exploring all the neighbors. The following lemma shows that the average runtime improves.
Lemma 4.1 ().
For a given vertex with outdegree in , the expected time to search its adjacent list to identify one or more distinct monotone staircases is .
Proof.
Since all the vertices in the neighborhood of
are equally probable to be picked, with a probability of
, the expected runtime to search a particular neighbor with random indexing is:=
=
∎
Alike the greedy method in (Kar et al., 2012) and Section 3, the best case scenario occurs when all the edges emanating from obey the monotone staircase property (Lemma 2.1), thus giving distinct monotone staircases. The worst case scenario occurs when the number of such edges is only , resulting in only one monotone staircase. The following lemma gives the average number of staircases can be explored by a single vertex .
Lemma 4.2 ().
For a given vertex with outdegree in , distinct monotone staircases can be identified while obeying Lemma 2.1.
Proof.
Since, all the edges emanating from have probability of obeying Lemma 2.1, the average case
=
=
Hence, distinct monotone staircases can be identified.
∎
4.1. The Pseudocode for the proposed randomized bipartitioner
In this section, we present the pseudocode for the proposed randomized floorplan bipartitioning method MSCut_Bend_RAND in Algorithm 3, in order to identify a minimal bend monotone staircase in a given floorplan at a given level of bipartition hierarchy. Alike Algorithm 1, this algorithm is called at any level of the bipartitioning hierarchy. The bipartition hierarchy is obtained by the same recursive framework presented in Algorithm 2.
Lemma 4.3 ().
The proposed randomized bipartitioning method MSCut_Bend_RAND takes time for obtaining an optimal monotone staircase with minimal bend count on BAG of a given floorplan .
Proof.
Since the number of edges in is and = , where is the outdegree of , it takes time for searching distinct monotone staircases. In this method, we use trials in order to obtain a different sequence of monotone staircases in each trial, but possibly not disjoint. Also the net partitioning procedure takes , while finding the number of bends account for time (see Lemma 3.1). Thus, the overall time taken by the proposed bipartitioning method is , i.e., . ∎
Note that Algorithm 3 has the same time complexity as Algorithm 1, but only a constant times higher due to multiple trials conducted for obtaining different sequences. In order to obtain a set of optimal monotone staircases with minimal bend count for the entire floorplan, the same recursive bipartitioning framework presented in Algorithm 2 can be used. Therefore, the recursive procedure considering the proposed randomized technique takes time to generate a hierarchy of monotone staircase cuts for a given floorplan topology.
5. Experimental Results
In order to verify the correctness and efficiency the proposed bipartitioning methods, we ran them on MCNC/GSRC floorplanning benchmark circuits (par, [n. d.]) (see Table 1). Different floorplan instances of a circuit were generated using Parquet floorplacement tool (Adya and Markov, 2003; par, [n. d.]) using random seeds. In order to observe different bipartitioning scenarios for the same circuit, we generated four different floorplan instances for each circuit. The algorithms were implemented in programming language and run on a Linux platform (GHz, GB RAM).
Suite  Circuit  #Blocks  #Nets  Avg. Net 
Degree  
MCNC  apte  9  44  3.500 
hp  11  44  3.545  
xerox  10  183  2.508  
ami33  33  84  4.154  
ami49  49  377  2.337  
GSRC  n10  10  54  2.129 
n30  30  147  2.102  
n50  50  320  2.112  
n100  100  576  2.135  
n200  200  1274  2.138  
n300  300  1632  2.161 
5.1. Bipartitioning Results
In our experimental setup, we ran the proposed monotone staircase bipartitioning methods with minimal bends, BFS (see Algorithm 1) and randomized (RAND) version (refer to Algorithm 3) that works in breadthfirst traversal (BFS) fashion at any node of the bipartition hierarchy (see Algorithm 2). For experimental purpose, we also came up with a variant of the BFS based greedy method by adopting depthfirst search (DFS) on the BAG. Due to lack of space, we are unable to present its pseudocode. An example showing the working of these bipartitioning methods (BFS, DFS, RAND) is presented in Appendix 7.1.
These experiments were conducted with , and ,, both varying in steps of such that . The corresponding bipartitioning results for BFS, DFS, and RAND methods are presented in Fig. 11 for: (a) area balance ratio (), (b) normalized bend count (), (c) normalized net cut (), and (d) (see Eqn. 1) respectively. The corresponding values were computed as an average of the respective parameters over the specified () pairs and all instances of a given circuit. We compare these results with an earlier BFS based directed search method (Kar et al., 2012) which did not consider bend minimization (BFSNB). It is also important to note that the results presented in (Kar et al., 2012) is for = only which is similar to the results for = and = case in BFS mode. Moreover, they did not report the individual objective values in their paper. For fair comparison, we ran their code (Kar et al., 2012) for obtaining the results for each of the objectives other than in BFSNB mode, including runtime.
The results on area balance in Fig. 11 (a) show that BFSNB (Kar et al., 2012) outperforms all other modes {BFS,DFS,RAND} that used bend minimization objective, by focusing on area balance and net cut only. Among the proposed methods, DFS has the worst area balance values for most of the circuits. For net cut, BFSNB mode performs well only for a few circuits although the net cut objective has more weight of for = . BFS and RAND have better net cut results for most of the circuits. Likewise, DFS mode continues to give higher net cut values for all the circuits. Regarding the number of bends, RAND mode is consistently better for most of the circuits compared to BFS and DFS. Due to certain floorplan topologies in specific circuits, DFS mode had better average values of bend counts for smaller circuits such as , , , with around blocks and large circuit . Lastly, BFSNB consistently yielded the worst (highest) bend counts over other modes. Overall, the values reported for each circuit show that BFSNB is the best for circuits up to , followed by RAND mode which dominates the values over BFS and DFS modes for the remaining circuits. For larger circuits like and above, RAND mode is seen to supersede BFSNB with the maximum values.
Due to balanced bipartitioning at each node of the bipartition hierarchy (MSC tree (Kar et al., 2012)), the height of the bipartition (MSC) tree is stated to be , where is the number of blocks in a floorplan. The results presented in Fig. 12 for each circuit shows that the average height of the MSC tree taken over the generated floorplan instances and (, ) values, is contained within the tight bounds of and , thus establishing the claim in Theorem 3.2.
Table 2 presents the runtime results for the proposed recursive floorplan bipartitioners (BFS, RAND and DFS) as well as (Kar et al., 2012) (BFSNB). As stated in Section 4, RAND mode is merely a constant times higher than the other two modes and is more prominent with larger circuits such as , and , while BFS/DFS report similar runtime for all the circuits. But, none of these methods can match the runtime values obtained by the faster method BFSNB as claimed by (Kar et al., 2012) even for the larger circuits.
Circuit  BFS  DFS  RAND  BFSNB (Kar et al., 2012) 

apte  0.005  0.005  0.007  0.005 
hp  0.006  0.005  0.009  0.003 
xerox  0.011  0.011  0.016  0.009 
ami33  0.033  0.032  0.060  0.014 
ami49  0.107  0.106  0.225  0.023 
n10  0.005  0.004  0.008  0.008 
n30  0.031  0.031  0.058  0.006 
n50  0.124  0.123  0.220  0.050 
n100  0.803  0.800  1.369  0.062 
n200  7.841  7.833  12.612  0.432 
n300  21.945  22.055  38.967  0.656 
Normalized  
Geo Mean  3.601  3.549  6.200  1.000 
5.2. Via Count in Early Global Routing by STAIRoute
In this section, we present the experimental results on early via estimation by performing early global routing of the corresponding floorplan level netlist using STAIRoute
(Kar et al., 2013) and the bipartitioning results presented in earlier subsection for BFS, DFS, and RAND modes. A maximum of metal layers were used by STAIRoute using preferred routing directions. We present the corresponding results for the largest benchmark circuit in Fig. 13 and 14 for and in steps of . This experimental setup does not apply to BFSNB mode since the corresponding values of () is not applicable for it. However, our study confirmed that the via count for BFSNB mode resembles that with BFS mode for = and = .We also study the variation of via count for two different floorplan instances of , the bestcase instance with smaller HPWL (Instance#1) and the worstcase instance with larger HPWL (Instance#2) in Fig. 13 and 14. In case of instance#1, DFS mode dominates over BFS and RAND modes only for = . However, cases show that RAND mode dominates DFS for upto some values, such as , and respectively, for the respective . Beyond these values, DFS yields the best via count for this floorplan instance of . In a very small range of and values, i.e., = and , BFS appears to dominate over DFS and RAND modes.
For the worst case instance, RAND gives smallest via count as compared to other modes for = and for . As increases, BFS dominates in lower values of , while RAND dominates for the remaining values with fewer via counts. For all values and the respective values, via count due to DFS mode is almost constant, with some variations near value of and .
The experiments on all benchmark circuits for different floorplan instances showed that there was no significant variation in routed netlength obtained for BFS, DFS and RAND modes, but are better than that obtained in BFSNB mode. Due to lack of space, we are not able to put the relevant details obtained by STAIRoute. These netlength values as normalized with resepect to noblockage aware steiner length (computed by FLUTE (Chu and Wong, 2008)
) ratio and their geometric mean values were obtained as
, and for BFS, DFS and RAND modes respectively, while BFSNB mode yields a value of . Using the approach in (Wei et al., 2012), the average worst case congestion, defined as the ratio of routing demand and routing capacity, for different floorplan instances of all the circuits in all the modes and for all () pairs, remained ensuring routability, using up to metal layers as per the congestion model proposed in STAIRoute (Kar et al., 2013). However, the maximum average congestion (Wei et al., 2012) in any of the floorplan instances for any mode and () values was seen to be . This shows that no monotone staircase routing region had a congestion over in any routing layer as claimed by (Kar et al., 2013).6. Conclusion
In this paper, we proposed an early version of unconstrained via minimization in floorplan based early global routing, by a new recursive floorplan bipartitioning framework. This bipartitioning framework identifies, for a given floorplan topology, a set of monotone staircase routing regions with minimal number of bends, by: (a) a greedy method employing BFS/DFS based graph search techniques, and (b) a randomized neighbor search technique for staircase wavefront propagation on BAG of the given floorplan. In this work, we first introduce the bend minimization objective in the multiobjective floorplan bipartitioning problem using monotone staircase cuts and used a pair of tradeoff parameters (). The solution of this optimization yields a minimal bend monotone staircase routing which impacts the via count during floorplan based early global routing.
Experimental results show the impact of the results of the proposed minimal bend monotone staircase bipartitioning methods on via count during early global routing for varying () pairs and yield fewer via counts. This framework can potentially assess the quality of the floorplan in terms of these via counts.
7. Appendix
7.1. Staircase Wavefront Propagation in a Floorplan
We consider an example of monotone staircase wavefront propagation in a floorplan instance for blocks, as depicted in Fig. 15. In this example, we study how different monotone staircase cuts on BAG can sequentially be obtained by the proposed DFS, BFS and randomized bipartitioning methods (RAND). This helps in exploring different sequences of monotone staircases with increased solution space for identifying an optimal monotone staircase for a given () pair.
Due to space limitation, only first few steps for identifying a sequence of monotone staircases obtained by BFS/DFS based bipartitioning are illustrated in Fig. 15 (a) and (b). It shows that both the methods greedily search the neighborhood of a vertex (block) in the BAG (see Fig. 10 (a)) for propagating the respective wavefronts. Fig. 15 (c)(e), illustrates three different trials of Algorithm 3 employing the proposed randomized neighbor search (see Fig. 10 (b)). The trials in RAND yield different wavefront propagation instances, as monotone staircase cuts on the BAG. It is important to note that BFS/DFS explores a fixed sequence of distinct staircases (see Lemma in (Kar et al., 2012)) for the same (, ) value, irrespective of the number of trials. On the other hand, RAND yields different sequences during different trials, by the proposed random neighbor indexing of the vertices. It is not necessary for the sequences to be fully disjoint as evident from Fig. 15 (c)(e). Despite that, an increased solution space of different monotone staircases (a union of all of them obtained during different trials in RAND mode) facilitates us to identify an optimal monotone staircase with minimal number of bends for a given (), implied by the maximum value.
7.2. Potential crosstalk minimization
This part discusses potential crosstalk minimization by minimizing the number of cut nets at any level of the bipartition hierarchy, MSC tree, by suitably choosing () pair, as illustrated in Fig. 16. In this example, we consider two instances of monotone staircases: (a) with more bends and net cut, and (b) with less bend and net cut, as depicted in Fig. 16 (a) and (b) respectively. In the former case, we see that two nets and are routed through the same monotone staircase routing region (MIS here) using same metal layer and therefore may results in signal cross talk among themselves. The latter case, however, shows that two different staircases are used to route nets and ; although net partly uses the same staircase (MIS), rest of its routing is done through a different staircase (MDS here). Therefore, both and will have minimal scope of signal interference between them.
References
 (1)
 has ([n. d.]) [n. d.]. Hasse Diagram, Wikipedia. ([n. d.]). https://en.wikipedia.org/wiki/Hasse_diagram
 oly ([n. d.]) [n. d.]. OlympusSoC tool, Mentor Graphics Inc. ([n. d.]). https://www.mentor.com/products/ic_nanometer_design/placeroute/olympussoc
 par ([n. d.]) [n. d.]. Parquet Floorplanner and MCNC/GSRC Floorplanning Benchmarks. ([n. d.]). https://vlsicad.eecs.umich.edu/BK/parquet
 Adya and Markov (2003) S. N. Adya and I. L. Markov. 2003. Fixedoutline floorplanning: Enabling hierarchical design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, 6 (Dec 2003), 1120–1135. https://doi.org/10.1109/TVLSI.2003.817546
 Cao et al. (2008) Z. Cao, T. T. Jing, J. Xiong, Y. Hu, Z Feng, L. He, and X. L. Hong. 2008. Fashion: A Fast and Accurate Solution to Global Routing Problem. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 27, 4 (April 2008), 726–737. https://doi.org/10.1109/TCAD.2008.917590
 Chang et al. (2003) C. C. Chang, J. Cong, Z. Pan, and X. Yuan. 2003. Multilevel global placement with congestion control. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 22, 4 (Apr 2003), 395–409. https://doi.org/10.1109/TCAD.2003.809661
 Chen and Chang (2009) H. Y. Chen and Y. W. Chang. 2009. Routing for manufacturability and reliability. IEEE Circuits and Systems Magazine 9, 3 (Third 2009), 20–31. https://doi.org/10.1109/MCAS.2009.933855
 Chien and Wang (2014) H. A. Chien and T. C. Wang. 2014. Redundantviaaware ECO routing. In 2014 19th Asia and South Pacific Design Automation Conference (ASPDAC). 418–423. https://doi.org/10.1109/ASPDAC.2014.6742927
 Cho et al. (2009) M. Cho, K. Lu, K. Yuan, and D. Z. Pan. 2009. BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability. ACM Trans. Des. Autom. Electron. Syst. 14, 2, Article 32 (April 2009), 21 pages. https://doi.org/10.1145/1497561.1497575
 Chu and Wong (2008) C. Chu and Y. C. Wong. 2008. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 27, 1 (Jan 2008), 70–83. https://doi.org/10.1109/TCAD.2007.907068
 Dasgupta et al. (2002) P. Dasgupta, P. Pan, S. C. Nandy, and B. B. Bhattacharya. 2002. Monotone Bipartitioning Problem in a Planar Point Set with Applications to VLSI. ACM Trans. Des. Autom. Electron. Syst. 7, 2 (April 2002), 231–248. https://doi.org/10.1145/544536.544537
 Guruswamy and Wong (1988) M. Guruswamy and D. F. Wong. 1988. Channel routing order for buildingblock layout with rectilinear modules. In IEEE International Conference on ComputerAided Design (ICCAD89) Digest of Technical Papers. 184–187. https://doi.org/10.1109/ICCAD.1988.122490
 He et al. (2013) X. He, T. Huang, W. K. Chow, J. Kuang, K. C. Lam, W. Cai, and E. F. Y. Young. 2013. Ripple 2.0: High quality routabilitydriven placement via global router integration. In Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE. 1–6.
 Hsu (1983) C. P. Hsu. 1983. MinimumVia Topological Routing. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 2, 4 (October 1983), 235–246. https://doi.org/10.1109/TCAD.1983.1270041
 Kar et al. (2013) B. Kar, S. SurKolay, and C. Mandal. 2013. STAIRoute: Global routing using monotone staircase channels. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 57, 2013. 90–95.
 Kar et al. (2014) B. Kar, S. SurKolay, and C. Mandal. 2014. Global Routing Using Monotone Staircases with Minimal Bends. In 2014 27th International Conference on VLSI Design, VLSID 2014, Mumbai, India, January 59, 2014. 369–374.
 Kar et al. (2015) B. Kar, S. SurKolay, and C. Mandal. 2015. A New Method for Defining Monotone Staircases in VLSI Floorplans. In 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 810, 2015. 107–112.
 Kar et al. (2012) B. Kar, S. SurKolay, S. H. Rangarajan, and C. Mandal. 2012. A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. In Progress in VLSI Design and Test  16th International Symposium, VDAT 2012, Shibpur, India, July 14, 2012. Proceedings. 327–336.
 Kastner et al. (2002) R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. 2002. Pattern routing: use and theory for increasing predictability and avoiding coupling. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 21, 7 (Jul 2002), 777–790. https://doi.org/10.1109/TCAD.2002.1013891
 Lee (1961) C.Y. Lee. 1961. An Algorithm for Path Connections and Its Applications. Electronic Computers, IRE Transactions on EC10, 3 (Sept 1961), 346–365. https://doi.org/10.1109/TEC.1961.5219222
 Lee and Wang (2008) T. H. Lee and T. C. Wang. 2008. CongestionConstrained Layer Assignment for Via Minimization in Global Routing. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 27, 9 (Sept 2008), 1643–1656. https://doi.org/10.1109/TCAD.2008.927733
 Lin and Chu (2014) T. Lin and C. Chu. 2014. POLAR 2.0: An effective routabilitydriven placer. In Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE. 1–6.
 Liu et al. (2013) W. H. Liu, C. K. Koh, and Y. L. Li. 2013. Optimization of placement solutions for routability. In Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE. 1–9.
 Lu and Sham (2013) J. Lu and C. W. Sham. 2013. LMgr: A lowMemory global router with dynamic topology update and bendingaware optimum path search. In Quality Electronic Design (ISQED), 2013 14th International Symposium on. 231–238. https://doi.org/10.1109/ISQED.2013.6523615
 Majumder et al. (2007) S. Majumder, S. SurKolay, B. B. Bhattacharya, and S. K. Das. 2007. Hierarchical partitioning of VLSI floorplans by staircases. ACM Trans. Design Autom. Electr. Syst. 12, 1 (2007). https://doi.org/10.1145/1217088.1217095
 Majumder et al. (2004) S. Majumder, S. SurKolay, S. C. Nandy, and B. B. Bhattacharya. 2004. On Finding a Staircase Channel with Minimum Crossing Nets in a VLSI Floorplan. Journal of Circuits, Systems and Computers 13, 05 (2004), 1019–1038. https://doi.org/10.1142/S0218126604001854 arXiv:http://www.worldscientific.com/doi/pdf/10.1142/S0218126604001854
 MarekSadowska (1984) M. MarekSadowska. 1984. An Unconstrained Topological Via Minimization Problem for TwoLayer Routing. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 3, 3 (July 1984), 184–190. https://doi.org/10.1109/TCAD.1984.1270074
 Pan and Chu (2006) M. Pan and C. Chu. 2006. FastRoute: A Step to Integrate Global Routing into Placement. In ComputerAided Design, 2006. ICCAD ’06. IEEE/ACM International Conference on. 464–471. https://doi.org/10.1109/ICCAD.2006.320159
 Pan and Chu (2007) M. Pan and C. Chu. 2007. IPR: An Integrated Placement and Routing Algorithm. In Design Automation Conference, 2007. DAC ’07. 44th ACM/IEEE. 59–62.
 Roy and Markov (2008) J.A. Roy and I.L. Markov. 2008. HighPerformance Routing at the Nanometer Scale. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 27, 6 (June 2008), 1066–1077. https://doi.org/10.1109/TCAD.2008.923255
 Sherwani (1995) N. A. Sherwani. 1995. Algorithms for VLSI Physical Design Automation (2nd ed.). Kluwer Academic Publishers, Norwell, MA, USA.
 SurKolay and Bhattacharya (1991) S. SurKolay and B. B. Bhattacharya. 1991. The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order. In IEEE International Conference on Computer Design: VLSI in Computers and Processors. 524–527. https://doi.org/10.1109/ICCD.1991.139964
 Viswanathan and Chu (2005) N. Viswanathan and C. Chu. 2005. FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model. ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on 24, 5 (May 2005), 722–733. https://doi.org/10.1109/TCAD.2005.846365
 Viswanathan et al. (2006) N. Viswanathan, M. Pan, and C. Chu. 2006. FastPlace 2.0: an efficient analytical placer for mixedmode designs. In Design Automation, 2006. Asia and South Pacific Conference on. 6 pp.–. https://doi.org/10.1109/ASPDAC.2006.1594681
 Wei et al. (2012) Y. Wei, C. Sze, N. Viswanathan, Z. Li, C.J. Alpert, L. Reddy, A.D. Huber, G.E. Tellez, D. Keller, and S.S. Sapatnekar. 2012. GLARE: Global and local wiring aware routability evaluation. In Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE. 768–773.
 Xu et al. (2009) Y. Xu, Y. Zhang, and C. Chu. 2009. FastRoute 4.0: Global router with efficient via minimization. In Design Automation Conference, 2009. ASPDAC 2009. Asia and South Pacific. 576–581. https://doi.org/10.1109/ASPDAC.2009.4796542
 Zhang and Chu (2012) Y. Zhang and C. Chu. 2012. GDRouter: Interleaved global routing and detailed routing for ultimate routability. In Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE. 597–602.
 Zhang et al. (2008) Y. Zhang, Y. Xu, and C. Chu. 2008. FastRoute3.0: A fast and high quality global router based on virtual capacity. In ComputerAided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on. 344–349. https://doi.org/10.1109/ICCAD.2008.4681596