Proliferation of intelligent connected technologies are opening venues to new service and computing models, providing diverse socio-economic benefits. These technologies are giving rise to wide range of intelligent applications including smart home, smart city, smart grid and intelligent transportation systems , 
. Estimates from market leading industry predict that intelligent connected technologies will proliferate to a trillion devices by 2035. This rapid growth of intelligent consumer and industrial solutions is leading to significant growth in smart embedded devices, such as wearables and critical infrastructure components, that provide information and communication functions to the users and businesses.
These smart embedded devices will be integrated and deployed in public and private environments for commercial and non-commercial purposes, to enhance business and consumer experiences by sharing and analysing generated data , 
. This data can be used in a variety of ways, enhancing the customer’s experience, bringing new business models and market opportunities using artificial intelligence, machine learning and data analytics, to make better informed decisions. However, where this sharing of data brings benefits and opportunities, it simultaneously presents risks. The large-scale integration and deployment of smart embedded devices and related services within critical infrastructure environments to control critical tasks, poses serious design, supply chain, security and safety challenges , , , .
As reliance on these technologies has grown, opportunities have arisen for adversaries to attack and compromise public and commercial critical infrastructure systems , , . Therefore, international government agencies have released cyber security regulations , ,  to curtail this problem by advocating businesses and technology manufacturers to comply and adhere to these regulations. These cyber security regulations pose a need for smart embedded devices and intelligent technologies to be Cyber Resilient. Device manufacturers therefore should design, develop and deploy security within their products to maintain compliance, consumer confidence and market share. However this need for harnessing security to comply with cyber security regulations, has compelled embedded designers and security architects to deploy defences that are often ad-hoc and passive in nature. As they have been designed to mitigate a certain class of known attacks . Nevertheless, this strategy has been found vulnerable and compromised due to software vulnerabilities, microarchitectural weaknesses and poor use of secure design practices , , , , , .
Open literature and reported events show that attack methods are evolving and becoming sophisticated, software vulnerabilities are inevitable, embedded architectures are insecure and are therefore susceptible to diverse attacks , . A successful launch of an attack on a device can expose private and confidential data of the user and enterprise to adversaries. To best of our knowledge, no existing embedded security microarchitecture or defence mechanism provides continuity of data stream and the information that can be extracted to gain and establish an evidence caused by the security breach for Cyber Forensics.
Considering these diverse cyber security challenges, there is a need for adopting a holistic rather than continue pursuing passive approach to achieve cyber resilience in embedded systems. The architecture shall harness, maintain and ensure design and operational security. Moreover, it shall be capable of both detection and recovery from a launched attack, and preserve crucial security requirements of embedded device deployed within public and private critical environments.
This paper will present the core security functions set out by the international security authorities in Section II. A comprehensive review of existing embedded security practices and mapping of core security functions to existing embedded security landscape will be presented in Section III which will be used to derive the security requirements of a cyber resilient embedded system. The shortcomings of well established embedded security microarchitectures will be discussed in Section IV and microarchitectural characteristics of a cyber resilient embedded system will be proposed in Section V.
Ii Cyber Resilience & Cyber Security Regulations
Currently, major differences exist in the way companies are using technologies and adopting security practices into their design, development and operational processes making it more difficult to mitigate and fight against cyber attacks . This problem has been elevated by the lack of adoption of security and cyber resilient posture by the stakeholders. IT Governance is a global provider of cyber risk and privacy management solutions that defines Cyber resilience  as:
”The ability of a system to identify, prevent, and respond to cyber attacks, intended to disrupt the system’s operational capabilities while maintaining confidentiality and integrity of the data”
To streamline these security issues, the National Institute of Standards and Technology (NIST) and the National Cyber Security Centre (NCSC) have released the following frameworks and regulations to improve security:
NIST Risk Management Framework (RMF)
NIST Cyber Security Framework (CSF)
NSCS Security of Network and Information Systems Regulations (NIS)
The NIST Risk Management Framework  is a guidance document designed to help organisations and enterprises assess and manage risks to their information and infrastructure. It enables a process that integrates security and risk management activities within the system development life cycle as shown in Figure 1. It provides means to select, implement, assess, authorise and monitor controls. This involves identification of critical components based on their security requirements followed by selection and implementation of effective monitoring controls, that are aligned with the system’s operational behaviour. This process enables security architects to identify risks, select suitable mitigation strategies and deploy countermeasures. This also avoid vulnerabilities which might be overlooked in product functional specification.
The NIST Cyber Security Framework  aims to improve the security of critical infrastructure from cyber attacks. It provides a set of guidelines for technology manufacturers to follow and better prepare to handle cyber attacks, particularly where a lack of security standardisation exists. The framework defines five core security functions (identify, detect, protect, respond and recover) to establish, maintain and improve cyber resilience as illustrated in Figure 1.
The primary focus of NCSC Security of Network and Information Systems (NIS)  regulation is to respond to rising cyber security challenges faced by public/private organisations and enterprises by minimising the risks of disruption to services caused by the failure of digital technologies. One of the key objectives is to establish and improve cyber resilience of intelligent technologies by identifying and managing risks of potential causes of failure by gaining and establishing an evidence of the caused security breach. For this purpose, the regulation introduces four security principles (managing security risks, protecting against cyber attacks, detecting cyber security incidents and minimising the impact of incidents) as shown in Figure 1.
The discussed frameworks and regulations advocates that it is essential for technology manufacturers and their involved partners, including semiconductor and original equipment manufacturers (OEMs), to manage their risks by implementing appropriate and proportionate embedded security measures for next-generation critical infrastructure.
|NSCS NIS||NIST CSF||Operational Security||Cyber Resilient||Existing Embedded Security Practices,|
|||||Requirements||Embedded Security Requirements||Methods and Microarchitectures|
|Asset Management||Embedded Security Modelling|
|Managing||• Understand and Assess||• Risk Assessment||
✪ STRIDE, PASTA, CVSS, DREAD, HARA
|Security||Identify||• Identify Risks||• Threat and Security Modelling||❖ IEC 61508, ISO2626 (ASIL A-D), ISO/IEC 15408|
|Risks||• Prioritise and Evaluate||• Attack surface identification||❖ Common Criteria, FIPS 140-2, ETSI TVRA|
|• Comply and Review||• Secure-by-design practises||❖ ISO/IEC 27005, SAE J3061, ISO/IEC 27001|
|Awareness Control||Protection Method|
|Protecting||• Protect Data||• Chain of Trust||Root of Trust, Trusted Technologies, ✪ Secure boot|
|against||Protect||• Protection Technology||• Data Confidentiality and Integrity||✪ AES, ECC, RSA, EDSA, ECCDSA, SHA, SSL|
|Cyber attack||• Manage & Adopt||• Secure Provisioning & Attestation||✪ Digital Certificate, Public-Private Key Infrastructure|
|• Isolation and Segregation||✪ ARM TrustZone, Intel SGX|
|Event Discovery||Detection Method|
|Detecting||• Discover & Determine||• Platform Security Architecture||✪ ARM Platform Security Architecture|
|Cyber Security||Detect||• Continuous Monitoring||• Trusted Execution Environment||✪ Global Platform, ARM TEE, QSEE, Kinibi|
|Incidents||• Detect Anomalies||• Static & Dynamic Flow Integrity||✪ Dover , ✹ ARMHEx |
|• Alert Events||• Access Control and Policing||✹ SECA |
|Response Planning||Response Method|
|• Analyse detected events||• Platform Security Manager||✪ Trusted Platform Module|
|Minimising the||Respond||• Response Strategy||• Physical Security||✪ Side-channel countermeasure|
|impact of||• Mitigation Strategy||• Passive countermeasure||✪ Reboot, Reset, Key zeroisation|
|• Report & Improve||• Active countermeasure|
|cyber security||Recovery Planning||Recovery Method|
|incidents||• Repair and Update||• Roll-back and Roll-forward||✪ Secure Firmware Update, On-the-air update|
|Recover||• Improve and Train||• Fault avoidance and tolerance||✪ Single event upset, Parity, Error Correction Codes|
|• Communicate||• Static and Dynamic Redundancy||✪ Hardware/Software redundancy, Process pairs|
|• Evidence Collection||• System Monitoring||✪ Voltage, clock and temperature monitors|
❖ International Standard ; ✪ Commercially Available ; ✹ Academic Research Frameworks/Solutions
Iii Security Requirements of
Cyber Resilient Embedded System
Cyber Resilience in embedded systems can be achieved by identifying the security requirements and incorporating them into the product life cycle. Intrinsically, the discussed Cyber Security regulations in Section II do not render security requirements for cyber resilient embedded system. Instead they yield a blueprint which can be used to articulate and derive security requirements for cyber resilient embedded system. Table I shows the association between NIS security principles and CSF core security functions and their operational security requirements. This includes asset management, awareness control, event discovery, response planning and recovery planning which are used to derive the security requirements of a cyber resilient embedded system. To bridge the research gap between information security and embedded security, the mapping of each driven embedded security requirement onto existing embedded security landscape is presented in Table I.
1⃝ IDENTIFY and manage cyber security risks by conducting asset management which involves detailed understanding of an application use case and respective deployment scenario. This requires decomposition of system components and evaluation of their interactions with internal and external entities to identify their associated risks and threats . This is followed by evaluating and prioritising tasks, where potential damage to the system and its infrastructure for each identified threat.
In embedded domain this process is well established which involves creating an abstraction of the embedded system  known as Threat and Security Modelling , . This builds profiles of a potential attacker, their goals and methods, which then used to define and deploy countermeasures either to mitigate, minimise the impact of the attack or making less attractive for an attacker. Table I list some of the risk and threat assessment modelling methods and international standards. They provide detailed guidelines and specifications to model, implement and comply diverse security in embedded systems.
2⃝ PROTECT against cyber attacks by introducing system awareness control. This required deployment of appropriate data security and protection methods to build a security foundation based on the principles of information assurance .
Confidentiality: Ensuring that information is disclosed only to intended individuals, entities and processes.
Integrity: Maintaining and assuring the accuracy and completeness of information over its life cycle.
Availability: Ensuring that information must be available when needed by individuals, entities and processes.
Authentication: Ensuring that information is accessible by only authorised individuals, entities and processes.
In the embedded security domain, well-established cryptography-based protection methods have been published as shown in Table I. These protection methods require strong trust anchor to establish and maintain confidentiality, integrity and authentication , , . In addition, embedded access control protection methods such as ARM TrustZone and Intel SGX have been widely used to achieve resource isolation and segregation by dividing system into subsystems and isolating their memory spaces.
3⃝ DETECT cyber security incidents using event discovery methods. This requires detection of malicious activity by continuous monitoring of system critical resources and comparing it against the healthy behaviour. Once malicious activity is detected, generate an alert to initiate a mitigation strategy.
In the embedded security domain, there is a significant published literature on signature, anomaly and information flow-based detection methods ,  as shown in Table I. Within embedded architectures, these security mechanisms have been deployed at hardware and software layers managed by a Trusted Execution Environment (TEE) .
4⃝ RESPOND to detected threats and malicious activities by planning and deploying an effective response and mitigation strategy to limit and reduce the impact of the cyber attack. Machine-to-Machine (M2M) communication is an enabling technology for critical infrastructure , which brought serious security challenges to secure, verify and avoid man-in-middle attacks in embedded systems. The existing embedded systems lack the capability to respond against attacks, making a need for active response against attacks a fundamental security requirement for cyber resilient embedded systems. Nevertheless, constantly evolving cyber attacks demand continuous re-evaluation for effective response and mitigation strategies.
Existing embedded security microarchitectures are largely focused on trust-based security and protection. They are limted and provide passive countermeasures such as watchdog timer, brownout reset, voltage and temperature monitoring and anti-tamper. Where, the vast majority system do not have any response mechanism and curtail such attacks using system reboot and reset. Nevertheless, trust management between device manufacturers and service providers is still a formidable challenge . Clearly, there is a strong need for embedded response methods and microarchitectures that fulfil the security requirements of cyber resilient embedded system.
5⃝ RECOVER system data and resources back to the device healthy provisioned state, by repairing, updating and patching the system. However, effective cyber strategy requires identification of the causes and method of system failure by collecting evidence from the compromised system. It allow to establish, conduct and communicate critical administrative tasks with the actors involved, during the system life cycle, to effectively ensure and maintain safety and security of the critical systems.
The existing embedded security architectures are limited to the principles of reliability to achieve recovery, and thus are insufficient to provide a system-level information or evidence that can be used to improve the cyber strategy. They often make use of fault avoidance and fault tolerant design practises by incorporating redundant system resources and roll-back patches to return the system to a healthy state.
Iv Challenges and Shortcomings in existing Embedded Security Micorarchitectures
Embedded Security has been the subject of extensive research in the context of general-purpose computing, signal processing, programmable architectures and communications systems , with significant published work on various fine and coarse grained embedded security challenges , , , . Security is often misapprehended by security architects and system designers as the addition of security features to make the system secure. Instead, security is a process that should be considered and managed throughout the life cycle of the embedded system specially for devices deployed in critical infrastructure. Therefore, this section first presents challenges of existing security microarchitectures:
The majority of embedded security microarchitectures follow Device Trust Architecture . It is a specification that provides a method to design and develop secure component technologies by building trust and secure services from the boot mechanism to the device operating system and application layer. Hence, the security of the system is strongly reliant on building and maintaining a strong chain of trust  which comprises of a series of nested assumptions and as vulnerable as its weakest link. If broken, compromises the security of the whole system. In the commercial domain, Secure Boot is a well established and widely used secure component, which has been found vulnerable , .
A lack of clear ownership of device security, insufficient adoption of security-aware practises and an absence of baseline security requirements. Practically design engineers do not perceive themselves accountable for security requirements and effectively embedding them into the device life cycle. This includes a lack of formal security risk assessment, with management of security technology outsourced to third parties for design, development and formalised security patch management process. As a result, this integration of third party services leads to security inconsistencies and vulnerabilities.
These challenges have posed immense need for harnessing security, in compliance with cyber security regulations. This in turn, has compelled embedded security architects to design and deploy defence mechanisms that are often ad-hoc and passive in nature, targeting and mitigating certain attacks or classes of attacks after they have been discovered . This approach may be effective to rectify software vulnerabilities or bugs through a software update, but insufficient to realise effective microarchitecture security which cannot be updated after release. The following are widely adopted embedded security methods has been found vulnerable due too poor usage of secure design practises, software vulnerabilities and microarchitectural weaknesses:
Trusted Computing: Trusted software services uses cryptographic digital signatures to verify the integrity of the firmware and applications which has been exploited to gain access to the device . This has occurred due to lack of roll-back prevention, as the system was using the same digital signature to verify the application. A similar attack has been performed against commercial TEE .
Processor virtualisation and logical isolation of resources: In existing embedded security architectures, processor virtualisation has been used to achieve logical isolation between secure and non-secure system resources. This has been attacked through a covert cache-based attack, resulting in leaking of information using microarchitecture side-channels. The recently demonstrated Spectre  attack leverage speculative loads which circumvent access checks to read memory-resident secrets, transmitting them to an attacker using cache timing or other covert communication channels. Meltdown  is another microarchitectural attack that exploits out-of-order execution to leak the target’s physical memory. These attacks exploit the fact that both secure and non-secure processes shares the same physical memory resource and pointer. Maene et al. have proposed a data encryption mechanism  that allows automatic encryption and decryption of data between the main memory and cache though found infeasible due to large area overhead.
Pointer Authentication: To circumvent the microarchitecture side-channel leakage attacks, a pointer authentication mechanism has been introduced . This guarantees the integrity of pointers by extending each pointer with authentication code, allowing verification using special instructions that are part of the code executing on the same physical computing resource and managed by the software. Similarly, to mitigate branch prediction attacks, deployment of separate stacks and their pointer registers has been introduced in ARM Cortex-M33 processors.
Vulnerable system communication: A security evaluation of the ARM TrustZone technology has demonstrated that it is possible to modify hardware security attributes and communication bus handshaking signals . This has demonstrated by integrating ARM TrustZone technology with reconfigurable hardware logic.
These microarchitectural weaknesses clearly indicates the need for cyber resilient embedded security microarchitecture that support active detection, response and recovery mechanisms to effectively realise diverse cyber security strategies through the life cycle of an embedded device. To this end, Section V proposes micro-architectural characteristics of a cyber resilient embedded system.
V Microarchitectural Characteristics of
a Cyber Resilient Embedded System
As discussed, there is no active method in existing embedded microarchitectures to establish and maintain the security of a device once its trust is compromised. This leads to exposure of confidential data to the adversary, often without leaving any evidence trail. Considering the derived security requirements of cyber resilient embedded system (Table I), security functionality is not limited to protection. The device must detect malicious cyber activities and attacks, respond against them by deploying active countermeasures and recover system back to its healthy state. These are crucial security requirements for embedded devices deployed in critical infrastructure as well as to facilitate forensic analysis, to study behaviour and method of cyber attacks. Using existing embedded security microarchitectures, this is difficult and implausible to recover data due to lack of continuity of data stream, runtime monitoring and system-level visibility. The following are proposed three core microarchitectural characteristics that shall allow to establish historical system data stream by continuous monitoring of system resources and activities, keeping track of events to achieve system-level visibility:
An Independent Active Runtime System Security Manager shall be responsible for protection, detection, response and recovery security functions while complimenting existing security mechanisms. It shall continuously monitor system resources, use gathered information to detect benign or malicious system behaviour, respond to detected malicious (system or resource-specific) activities by deploying active countermeasures and recover system back to its healthy state. It is crucial that system security manager must be physically independent and isolated so its memory resources from the general purpose processor. This physical limiting of attack surface, will make the system robust and significantly less susceptible to software vulnerabilities and attacks as was in the case of the TEE. As TEE shares the same physical processor and memory resources with the general purpose processor. Effective realisation of this system security manager requires resource-level visibility and monitoring of system’s critical components which leads to the second characteristic.
An Active Runtime Resource Monitors shall actively monitor resource specific behaviour to detect malicious activity and report it to the System Security Manager. These active monitors are essential as embedded architectures are becoming complex, designers are consolidating diverse functionalities into a single application often involves mixing of sensitive data with non-sensitive data and physical actuation. These active monitors shall generate fine-grained resource specific information which would enable the system security manager to articulate, analyse and evaluate system-level behaviours and initiate appropriate response and recovery strategies. In addition, this gathered information would facilitate continuity of data stream and to extract crucial information necessary to establish evidence of the caused security breach.
An Active Response Manager shall be responsible for implementing response and recovery embedded security requirements of a cyber resilient embedded system. It shall actively enforce and execute the response and recovery strategies initiated by the System Security Manager. This involves initiating active countermeasures to mitigate and curtail the detected threat to maintain and ensure security of the system. Moreover, depending on the microarchitecture of the active runtime resource monitors, the active response manager can enforce various system-level security strategies, where a compromised resource can be physically isolated from the system. This would allow opportunities to gracefully degrade the system functionality while maintaining critical services in next-generation critical infrastructure.
This paper has presented the increasing security challenges and requirements, in light of international cyber security regulations for intelligent connected technologies deployed in critical infrastructure. Embedded security requirements has been derived from these regulations to improve cyber resilience and achieve conformance. The paper establishes a strong need for embedded cyber resilience for smart technologies, due to lack of active detection, response and recovery security functionalities within existing embedded security systems.
This is due to the majority of embedded security technologies being guided by trust, which has been compromised due to a lack of runtime monitoring and system-level visibility of resources and system activities. Therefore, this paper proposed three embedded microarchitectural characteristics, allowing independent active runtime system monitoring and active response functions to enhance, maintain and ensure secure operation during the life cycle of the device.
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