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eSampling: Energy Harvesting ADCs

07/16/2020
by   Neha Jain, et al.
IISER Bhopal
Weizmann Institute of Science
IIIT Delhi
0

Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. The power consumed in conversion grows with the sampling rate and quantization resolution, imposing a major challenge in power-limited systems. A common ADC architecture is based on sample-and-hold (S/H) circuits, where the analog signal is being tracked only for a fraction of the sampling period. In this paper, we propose the concept of eSampling ADCs, which harvest energy from the analog signal during the time periods where the signal is not being tracked. This harvested energy can be used to supplement the ADC itself, paving the way to the possibility of zero-power consumption and power-saving ADCs. We analyze the tradeoff between the ability to recover the sampled signal and the energy harvested, and provide guidelines for setting the sampling rate in the light of accuracy and energy constraints. Our analysis indicates that eSampling ADCs operating with up to 12 bits per sample can acquire bandlimited analog signals such that they can be perfectly recovered without requiring power from the external source. Furthermore, our theoretical results reveal that eSampling ADCs can in fact save power by harvesting more energy than they consume. To verify the feasibility of eSampling ADCs, we present a circuit-level design using standard complementary metal oxide semiconductor (CMOS) 65 nm technology. An eSampling 8-bit ADC which samples at 40 MHZ is designed on a Cadence Virtuoso platform. Our experimental study involving Nyquist rate sampling of bandlimited signals demonstrates that such ADCs are indeed capable of harvesting more energy than that spent during analog-to-digital conversion, without affecting the accuracy.

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I Introduction

Physical signals are analog in nature, taking values in continuous sets over a continuous time interval. In order to process and extract information from such signals using digital hardware, they must be accurately represented in digital form. Analog-to-digital converters (ADCs) thus play an important role in digital signal processing systems [eldar2015sampling]. ADCs are typically a major source of energy consumption, as their power dissipation grows with the sampling rate and the quantization resolution, and thus their ability to accurately represent the acquired signal is typically limited by the available power [4403893]. Nowadays, ADCs are utilized in a multitude of energy-limited systems, including communication devices [shi2002data], wireless sensors [jain2018ideg], and medically implanted devices [6774474]. Therefore, there is a growing need for ADCs capable of reliably acquiring signals while consuming low power.

The existing strategies proposed in the literature to facilitate energy efficient acquisition of analog signal can be divided into those taking a signal processing approach, and techniques focusing on circuit level design. Signal processing approaches typically aim for allowing the ADC to operate at reduced sampling rate and quantization resolution by accounting for how the acquired signal is processed and prior information on the signal itself [michaeli2011xampling, cohen2018analog, cohen2018sub, shlezinger2019joint, jain2018ideg]. Additionally, in scenarios where the signal is acquired for some task, i.e., to recover some underlying information, it was recently shown that the desired information could be accurately recovered from the output of low-resolution ADCs by properly designing the acquisition system [shlezinger2018hardware, shlezinger2019deep, shlezinger2020learning, shlezinger2020task]. An alternative signal processing oriented method which does not limit the rate and resolution of ADC is based on acquiring a portion of the analog signal to be processed while utilizing the remaining part for energy harvesting. This strategy, typically studied in the context of communication receivers as simultaneous wireless information and power transfer (SWIPT), considers time or power splitting of the analog signal [6489506, 6503739, liu2013wireless, lu2014wireless]. However, it induces some inevitable loss on the system performance as only a portion of the signal is converted into a digital representation. These aforementioned signal processing methods typically focus on the signal model and the task for which it is acquired, without accounting for the ADC circuitry.

Circuit level methods rely on the hardware architecture of ADC devices. The circuit level approach generally considers designing energy efficient ADC circuitry, which is capable of operating with reduced power consumption. This can be achieved by reducing the circuit power supply [6774474] and/or limiting the operating frequency [artan2012optimizing] in order to reduce the overall power consumption. An alternative technique is to modify the circuit components in existing ADC architectures and combine various designs in the acquisition, such as sample-and-hold (S/H) ADCs, flash ADCs, sigma-delta ADCs, and time-interleaved ADCs, to improve their energy efficiency, see, e.g., [6936944, 8727467, 8676062, 8017456]. Such circuit-oriented designs which focus on the hardware aspects of acquisition, do not account for the model of the analog signal and the task for which it is acquired.

A popular power efficient ADC is the S/H based successive approximation register (SAR) architecture, which is capable of operating at high resolution and a small form factor with relatively low power consumption [razavi1995principles]. The power consumption of SAR ADCs can be further reduced by incorporating energy efficient switching schemes, as proposed in [hariprasath2010merged, liu201010]. In S/H architectures, the circuit used to sample the input analog signal consists of two phases, acquisition phase and hold phase in each sampling period. In the acquisition phase, the S/H circuit tracks the input analog signal. The sampled value captured in the acquisition phase is then converted into digital form, i.e., a sequence of bits, during hold phase. Therefore, during the sampling process of S/H ADCs, the input signal is processed only for a fraction of the overall sampling period (acquisition phase) and is neglected/discarded for the remaining time interval (hold phase) [1464555, mccreary1975all]. The fact that the signal is not accessed in a dominant portion of the sampling period, motivates the extension of S/H ADCs, and particularly S/H SAR ADCs, to continuously utilize the analog signal in order to mitigate power consumption.

In this work, we combine signal processing tools with circuit level methods to propose an eSampling ADC, which harvests energy from the acquired signal while converting it into a digital representation. The eSampling ADC builds upon the S/H ADC architecture while introducing an additional energy harvesting circuit. In the resulting architecture, the signal is harvested during hold phase, i.e., when it is not utilized in conventional S/H ADCs. This operation allows eSampling ADCs to harvest energy from the sampled signal without altering the conversion procedure. Our analysis of eSampling ADCs formulates the theoretical foundations for joint acquisition and energy harvesting, and generalizes the experimental results of our previous work [jainExp2020], which demonstrated that energy harvesting can be combined with sensing circuits. As opposed to SWIPT systems, in which the overall operation of the system is modified to allow energy harvesting while conventional ideal ADCs are assumed [lu2014wireless], eSampling exploits an inherent property of ADC devices to harvest energy as a natural byproduct of their hardware architecture. This makes eSampling an attractive technology which can be easily incorporated into existing devices.

Our theoretical study of eSampling ADCs analyzes its potential in terms of the ability to harvest energy while maintaining a desired accuracy of signal reconstruction. To that aim, we focus on the acquisition of stationary random processes and characterize the resulting tradeoff between the ability to accurately reconstruct the signal from its samples and the energy harvested from it, referred to henceforth as the energy-fidelity tradeoff. Our analysis identifies how to set the sampling rate to optimize this tradeoff when operating under energy constraints or fidelity restrictions on the reconstruction. The results allow us to numerically characterize the maximal accuracy in which any signal can be eSampled using only harvested energy, i.e., without requiring any energy from its power source. The energy consumed in acquisition is determined by the specific components comprising the ADC circuit. We show that eSampling ADCs operating with a typical set of ADC parameters are capable of fully reconstructing signals of various power spectral density (PSD) profiles with negligible distortion, while harvesting at least as much energy as they consume. In particular, we show that an eSampling ADC with bits quantization can acquire a bandlimited signal at the Nyquist rate while harvesting more energy than it consumes.

We then proceed to illustrate the hardware feasibility of such a device. To that aim, we design the circuitry of an eSampling 8-bit SAR ADC which samples at 40 MHz on 65 nm complementary metal oxide semiconductor (CMOS) technology, and provide guidelines for setting its parameters to achieve a desired amount of harvested energy. The experimental evaluation of the eSampling SAR ADC circuit, carried out on the Cadence Virtuoso platform, shows that the amount of energy harvested can be much larger than the amount of energy consumed during the conversion procedure. This is achieved without affecting the signal reconstruction accuracy when acquiring a bandlimited signal while satisfying Nyquist condition. Our experiment indicates that the theoretical potential of eSampling can be translated into an actual ADC circuit, which accurately acquires analog signals while harvesting more power than it consumes.

The rest of this paper is organized as follows: In Section II, we present our eSampling system model. Section III analyzes the associated energy-fidelity tradeoff. The circuit-level design and its experimental study are presented in Section IV. Finally, Section V provides concluding remarks.

[width=]samp_conv_transaction.pdf

Figure 1: S/H SAR ADC illustration: (a) acquisition phase (b) hold phase.

Ii System Model

In this section, we detail the proposed ADC model from a high-level perspective. We begin by briefly reviewing S/H-based SAR ADCs and their associated energy consumption in Subsection II-A. Then, we present how S/H ADCs can be extended into eSampling ADCs which harvest energy in addition to signal acquisition in Subsection II-B.

Ii-a Sample-and-Hold ADC Model

Ii-A1 High-level description

S/H is a common ADC architecture. Such ADCs acquire each sample in two phases, determined by a switch , as illustrated in Fig. 1: In the acquisition phase, the signal is connected to a capacitor , referred to as a holding capacitor, which is charged to the input analog voltage, as depicted in Fig. 1(a). The time required by the holding capacitor to charge to the input voltage, which dictates the acquisition time, is given by [razavi1995principles]

(1)

where is the on-resistance of the switch , and is the number of time constants, i.e., required for the capacitor to be fully charged.

Once the acquisition phase is over, the hold phase begins, in which the discrete sample, i.e., the voltage stored in the holding capacitor, is quantized into digital bits. During hold phase, whose duration is denoted by , the input signal is disconnected from the S/H circuit and holds the acquired voltage to accomplish the successful conversion of the acquired sample into digital bits as illustrated in Fig. 1(b). Both and , must be set to allow the quantization circuit of the ADC to complete the conversion.

When the quantizer is based on SAR logic, the overall architecture is referred to as a SAR ADC. An -bit SAR ADC consists of a comparator, digital-to-analog converter (DAC), and a SAR logical circuit which successively refines the digital representation. To allow successful quantization into bits, the hold time required to quantize each sample must satisfy [mccreary1975all]

(2)

where is the equivalent resistance of the quantizer binary scale switches. Therefore, the sampling period, i.e., the duration of acquiring a single sample, is lower bounded by the following expression

(3)

In S/H SAR ADCs, the on-resistance of the switch is commonly not larger than the resistance of the quantizer binary scale switches . Thus from (1) and (2), it is evident that is typically much larger than , particularly when using high resolution quantizers, such as ADCs with bits. Consequently, the input signal, which is tracked only during the acquisition phase, is discarded during most of the sampling period.

Ii-A2 Energy consumption

In general, the energy consumption of a circuit is typically a function of the time duration it is active, and the amount of power drawn from the supply, denoted here by . As is typically much larger than , most of the energy required by S/H SAR ADCs is consumed during hold phase [mccreary1975all, hariprasath2010merged].

In particular, the only energy consumed during acquisition phase, denoted , is that needed to toggle the sampling switch . In contrast, the energy consumption during hold phase, denoted , is comprised of the energy used by each of the components taking part in the quantization:

(4)

where , , and are the energy consumption of the DAC array, comparator, and SAR logic, respectively. Consequently, effectively represents the power consumed per sample by S/H SAR ADCs [mccreary1975all, hariprasath2010merged]. We elaborate on the quantities in (4), which are dictated by the specific circuit parameters used, in Section IV where a concrete circuit-level design is discussed. Here, we note that typically takes the form of a second-order polynomial in the reference voltage [6043594], i.e.,

(5)

The coefficients and in (5) are positive constants determined by the number of bits and the quantization circuit parameters, and can grow dramatically with . This makes energy consumption a major bottleneck of high resolution ADCs, motivating the proposed eSampling architecture detailed next.

Ii-B eSampling ADC Architecture

As mentioned above, during hold phase, the capacitor holds the acquired voltage sample, which is converted into a set of digital bits. In this interval, the input signal is disconnected from the circuit by the switch . In order to mitigate the energy consumption of S/H SAR ADCs without modifying their sampling and quantization procedure, we propose to harvest the input signal energy by connecting it to an energy harvesting circuit during the hold phase, as illustrated in Fig. 2. Henceforth, the proposed architecture is referred to eSampling ADC.

As depicted in Fig. 2, the energy harvesting capability is enabled by passing the signal observed during hold time through a conditioning circuit, whose output is used to charge an energy harvesting capacitor to a voltage level . The energy harvesting circuit can be designed using passive elements, as we do in our proposed design detailed in Section IV. Hence, no external power supply is required [7404333]. The purpose of the signal conditioning circuit used in energy harvesting devices is to facilitate the storage of the energy of the signal in the capacitor [8410909, 8740972, 7081797]. For instance, a rectifier can act as a signal conditioning circuit, reducing fluctuations in the amount of energy harvested in the presence of alternating signals. Similarly, voltage regulator circuits and DC-DC step up converters can also be used to enhance the overall efficiency of the energy harvesting system [sarker2013designing]. The common measure for the quality of an energy harvesting circuit is the efficiency parameter, denoted by , which represents the fraction of the energy of the input signal that is harvested. Finally, in order to connect the input signal to the quantization circuit during acquisition time and to the energy harvesting circuit during hold time, the sampling switch is replaced by a two-way switch . A possible circuit design such a two-way switch is detailed in Section IV.

The amount of energy consumed in acquisition phase given in (5) is dictated by the design parameters of the circuitry, which also affect the sampling rate via (3). In particular, the sampling duration is the sum of the acquisition time and the hold time . Further, the amount of time during which energy is harvested from the input signal per sampling period is at most . Recalling that typically , a significant portion of the sampling interval can be allocated for harvesting energy from the input signal. Since energy is only harvested during hold time, in which conventional S/H ADCs do not utilize the analog signal, the ability to harvest energy in eSampling ADCs does not affect the acquisition operation. Specifically, for a given sampling rate, eSampling ADCs implement the same conversion mapping as standard S/H ADCs operating at the same rate. Nonetheless, eSampling provides the ability to trade acquisition accuracy for harvesting more energy. This is due to the fact that increasing the sampling interval allows eSampling ADCs to dedicate more time to energy harvesting, possibly at the cost of degrading the accuracy in reconstructing the analog signal from its digital representation.

The goal of our analysis of eSampling ADCs presented in the following section is to quantify the theoretical potential benefits of such an architecture, which is capable of simultaneously acquiring analog signals into a digital form while harvesting their energy. Both the amount of energy consumed in conversion and that harvested in eSampling are determined by the specific circuitry, encapsulated in (5) and the energy efficiency parameter , respectively. Therefore, in our analysis we fix the circuit parameters, e.g., , , , etc., and express how the accuracy in reconstruction and the amount of energy harvested vary as the sampling interval changes. We are particularly interested in characterizing the amount of energy harvested in the regime in which the distortion induced by S/H conversion is negligible, e.g., Nyquist rate sampling of bandlimited signals, and understanding when is it possible for eSampling ADCs to operate at this regime while harvesting at least as much energy as they consume. Our theoretical analysis detailed in the sequel reveals that such a regime of operation is indeed feasible with typical ADC circuit parameters when acquiring bandlimited signals while using up to bits per sample.

Iii eSampling ADC Analysis

In this section, we analyze the capabilities of the proposed eSampling ADC in terms of the amount of energy one can harvest while meeting a given level of reconstruction accuracy, as well as the achievable accuracy for harvesting a desired amount of energy. The interplay between these key performance measures is determined by the selection of the sampling rate, as we show in the following. We begin by formulating the signal model under which our analysis is carried out, and the corresponding problem of characterizing the associated energy-fidelity tradeoff, which arises from the eSampling ADC paradigm in Subsection III-A. Then, we derive the achieved normalized mean-squared error (NMSE) under the considered model in Subsection III-B. The derived NMSE is used to characterize the energy-fidelity tradeoff in Subsection III-C, and to obtain as a special case the maximal amount of energy which can be harvested when sampling a bandlimited signal at a rate satisfying the Nyquist condition, i.e., allowing perfect recovery. We demonstrate a few examples of energy-fidelity tradeoff curves for signals with different spectral profiles in Subsection III-D. Finally, we discuss the pros and cons of eSampling ADC in light of our analysis in Subsection III-E.

Iii-a Problem Formulation

The eSampling ADC detailed in Subsection II-B harvests energy during hold phase. This implies that more energy can be harvested by increasing the hold time, which in turn increases the sampling period, potentially degrading the ability to reconstruct the signal from its samples. Therefore, to unveil the potential of eSampling ADCs, we first wish to analyze the fundamental tradeoff between the amount of energy harvested in eSampling and the resulting fidelity in signal reconstruction. We are particularly interested in: Quantifying the maximum amount of energy that could be harvested when acquiring bandlimited signals at the Nyquist rate, i.e., without compromising the signal reconstruction accuracy; and Characterizing the achievable NMSE when the ADC harvests at least as much power as it consumes.

In the analysis carried out in this section we consider a stochastic input signal

modeled as a zero-mean wide sense stationary (WSS) process, with variance

, and PSD . The signal is sampled uniformly with sampling interval , resulting in the discrete-time signal , , where is the set of integers. The sampled series is quantized with bits per sample into the digital sequence . The digital representation is utilized to recover the analog signal using a linear reconstruction filter , which is designed to minimize the NMSE between and the recovered signal as in [michaeli2008high, shlezinger2019joint]. The reconstructed signal is

(6)

The overall system is illustrated in Fig. 3.

[width=0.65]samp_eh_transaction.pdf

Figure 2: Proposed eSampling ADC system model.

The NMSE in reconstructing from is given by

(7)

where is the stochastic expectation. The amount of expected energy harvested per sampling period is given by

(8)

where and is the efficiency and the resistance of the energy harvesting circuit, respectively. As mentioned above, the energy harvesting circuit is comprised of passive elements, and does not require an external power source. Therefore, the overall energy consumption per sample using the proposed eSampling ADC can be given as as illustrated in Fig. 3. Recall that the overall energy consumption is typically dominated by the energy used during hold phase, i.e., , and hence the ratio of the amount of energy harvested to the energy consumption per sample can be approximated as . The value of is dictated by the power supply voltage and the number of quantization bits , as well as the SAR architecture and circuit parameters, as we show for our design detailed in Section IV.

In the following subsections, we study the fundamental tradeoff between the reconstruction accuracy, modelled as the NMSE, and the portion of the energy consumed in analog-to-digital conversion to that harvested by eSampling, referred to as the energy-fidelity tradeoff. To trade energy efficiency for fidelity, we modify the sampling rate for a fixed quantization resolution and fixed acquisition time . The reconstruction accuracy can be improved by increasing the sampling rate, however eSampling ADC will harvest less energy, and hence the inherent tradeoff between these parameters. In particular, we focus on ADCs operating with relatively high resolution, where energy consumption constitutes a major challenge. The following analysis sheds light on the potential of joint acquisition and energy harvesting. For example, it quantifies the minimal recovery NMSE which allows a fixed -bit ADC to operate at zero power, i.e., . Alternatively, it allows identifying the quantization resolution for which the eSampling ADC can sample a bandlimited signal at Nyquist condition and operate at zero power. For instance, we use our results to show that bandlimited signals can be eSampled at Nyquist rate with up to bits per sample while harvesting more energy than that consumed. Finally, the characterization of the energy-fidelity tradeoff allows computing the maximal amount of energy which can be harvested for an allowed level of reconstruction accuracy for both bandlimited and non-bandlimited signals, as a function of the ADC circuitry parameters.

[width=0.65]esampler.pdf

Figure 3: Acquisition and reconstruction via eSampling ADC illustration.

Iii-B Reconstruction NMSE

In general, the NMSE depends on both the sampling rate as well as the quantization resolution [kipnis2018fundamental]. Since we focus on relatively high rate quantization, the NMSE due to quantization is well-approximated by the dB rule-of-thumb [polyanskiy2014lecture, Ch. 23], and is thus on the order of [razavi1995principles], resulting in a negligible contribution to the overall NMSE of less than roughly for . Therefore, henceforth the focus is on the the NMSE between and due to the sampling procedure alone, expressed in the following theorem, derived in [michaeli2008high]:

Theorem 1

The minimal achievable NMSE in reconstructing a uniformly sampled WSS signal with sampling frequency using a linear reconstruction filter, is

(9)

To achieve (9), the linear recovery filter in (6) is set according to [michaeli2008high, shlezinger2019joint], i.e., its frequency response should be set to , where

denotes the Fourier transform. This digital filter setting results in the minimal achievable NMSE between

and . Theorem 1 generalizes the celebrated Shannon-Nyquist theorem, as stated in the following corollary:

Corollary 1

When is bandlimited and the sampling frequency satisfies Nyquist condition, the resulting NMSE is zero.

Proof:

If is bandlimited, then there exists some finite such that for all . When the sampling rate satisfies Nyquist condition, then . Consequently, the summands in (9) are non-zero only at , and hence

(10)

proving the corollary.

We next give an example of how Theorem 1 is computed:

Example 1

Consider a bandlimited signal whose spectral support is for some with flat PSD. The obtained NMSE for such signals computed via Theorem 1 is given by

(11)

Fig. 4 illustrates of the recovery NMSE result in Theorem 1, showing which spectral portions of a signal with a flat PSD as in Example 1 are preserved by the NMSE minimizing reconstruction. In particular, Fig. 4 demonstrates how the complete spectrum is preserved when sampling above Nyquist rate, while sub-Nyquist sampling yields some recovery error due to aliased components. Fig. 4 also depicts the amount of energy harvested from the signal based on (8), showing that reduction in the sampling rate allows to harvest more energy in eSampling at the cost of less accurate recovery, leading to the energy-fidelity tradeoff of eSampling analyzed in the sequel.

[width=0.8]eSampling1.png

Figure 4: Illustration of eSampling of a signal with a flat PSD for: (a) Sampling at Nyquist rate, while harvesting an amount of energy proportional to ; (b) Sampling at sub-Nyquist rate, thus trading recovery accuracy for harvesting more energy.

Iii-C Energy-Fidelity Tradeoff

In order to express the energy consumed in acquisition, we must first specify the voltage of the power supply

. This value should be larger than the amplitude of the input signal with high probability to avoid overloading the ADC. Consequently, in the following we write the value of

as some multiple

of the input standard deviation, i.e., the supply voltage is written as

. This general formulation allows us to relate the reference voltage with the overload probability of the quantizer, since the overload probability satisfies by Chebyshev’s inequality [shlezinger2018hardware]. Therefore, the ratio between the expected energy harvested (8) and consumed (5) for eSampling of a WSS signal can be written as

(12)

Recall that for a fixed sampling interval, eSampling ADCs implement the same conversion mapping as conventional S/H ADCs. Consequently, when one does not account for the distortion induced in quantization as we do here, WSS signals acquired by an eSampling ADC operating with sampling interval can be recovered with the NMSE stated in Theorem 1. We therefore use the expressions for the achievable NMSE (9) and the energy ratio (12) to characterize the energy-fidelity tradeoff of eSampling.

Under the considered setting, we formulate how the recovery accuracy and the energy ratio behave as the sampling period varies. Recalling that the acquisition time is determined by the ADC circuit parameters (1), modifying the sampling period is equivalent to tuning the hold time . The energy-fidelity tradeoff of eSampling is thus encapsulated in two complementary optimization problems: The first aims at finding the minimal achievable NMSE under a given energy constraint , i.e.,

(13)

Setting dB, implies that . Therefore, solving (13) with dB reveals the minimal NMSE achievable by an eSampling ADC which harvests at least as much energy as it consumes, i.e., when operating at zero power. A positive value of (in dB) implies an energy saving ADC which harvests more energy than its consumption per sample, namely, converting the signal only adds power to the system.

An alternative formulation seeks to maximize the energy harvested under a given fidelity constraint , i.e.,

(14)

For instance, consider a bandlimited signal. In such a case, one can achieve by eSampling at Nyquist rate, and harvest energy ratio , i.e., the maximal ratio of the harvested to energy to the consumed one when seeking ideal recovery. For non-bandlimited signals, approaching zero NMSE generally requires infinitesimally small sampling interval, which is not feasible due to the lower bound on dictated by the ADC circuity in (3). Consequently, when acquiring non-bandlimited signals (or extremely wideband signals), one would typically be more interested in evaluating (14) for some small yet feasible NMSE bound .

Problems (13)-(14) allow to characterize the energy-fidelity tradeoff, stated in the following theorem:

Theorem 2
Let be given by
By setting , the solution to (13) is
(15a)
Similarly, by letting be the maximal sampling interval satisfying in (9), then the solution to (14) is
(15b)
Proof:

The theorem follows by noting that in (9) is monotonically decreasing in , while in (12) is a monotonically increasing function of . Consequently, both (13) and (14) are obtained by identifying the minimal/maximal value of for which the constraint holds with equality, hence proving the theorem.

In the following subsection we provide a few examples of energy-fidelity tradeoffs which arise from the above analysis.

Iii-D Examples

The characterization of the energy-fidelity tradeoff in Theorem 2 identifies the achievable energy ratio for a given recovery accuracy and vice versa. It also reveals the achievable energy ratio when eSampling a bandlimited signal of maximum frequency with zero reconstruction error. In particular, combining Corollary 1 and Theorem 2 indicates that this energy ratio is given by

(16)

An example of how Theorem 2 is computed for arbitrary sampling rates is given in the following:

Example 2 (Flat PSD)

Consider again the bandlimited signal with flat PSD of Example 1. In this case, by (11), an NMSE of is guaranteed by using . Consequently, by Theorem 2 the energy ratio under fidelity constraint for such signals is given by

(17)

The resulting energy-fidelity tradeoff curve for different numbers of quantization bits is depicted in Fig. 5 under the following settings: We use , guaranteeing a probability of over 95% that , while the ADC circuit parameters are set to MHz, ns, fF, fF, fF, , , V, , V, , and . Finally, the signal power is accordingly set to .

[width=0.65]FlatPSD.png

Figure 5: NMSE () versus , flat PSD.

The specific design parameters used in evaluating Fig. 5 correspond to the eSampling ADC circuit design presented in Section IV, and are in the typical ranges provided in previous works on ADC circuitry, e.g., [6043594, 4588351, Craninckx2007A60]. The efficiency of the energy harvesting system is in line with similar values reported for energy harvesting circuits in [5117948, 5599946, 7792628].

As expected, the achievable energy ratio in Example 2 coincides with (16) when perfect recovery is required, i.e., . The energy ratio characterized in (17) is increased by reducing the sampling rate, which in turn increases the reconstruction error, , as illustrated in Fig. 4. The fundamental balance between these measures follows from the structure of eSampling ADCs, in which increasing the hold time degrades the ability to recover the signal from its samples, while allowing to harvest more energy. This unique property of eSampling can lead to ADCs which harvest more power than they consume, as observed in Fig. 5.

The results shown in Fig. 5 demonstrate that an eSampling ADC with up to bits acquiring a bandlimited signal can harvest more power than it consumes while sampling at Nyquist condition, and hence achieving zero-approaching reconstruction error. While the ability of eSampling ADCs to sample at Nyquist rate and zero-power is observed in Fig. 5 for signals with flat PSDs, it holds for arbitrary PSD shapes as long it is bandlimited to and the variance of the signal is . This follows since by (12), the energy ratio for a given sampling rate and signal variance does not depend on the shape of the PSD. However, for the ADC to operate at zero power with higher resolution quantization, one has to sample below the Nyquist rate and hence compromise in reconstruction error. In particular, each of the curves in Fig. 5 reaches zero NMSE for , while reducing the sampling rate allows achieving improved energy ratio at the cost of reduced reconstruction accuracy, reaching poor recovery performance of as is reduced to . It is emphasized that for a given sampling rate, eSampling ADCs implement the same acquisition mapping as conventional S/H ADCs, and thus their the ability to harvest energy using eSampling ADCs does not come at the expense of conversion accuracy. However, eSampling provides to possibility to increase the amount of energy harvested by increasing the sampling interval, which in turn may degrade the ability to recover the analog signal.

As discussed above, while the recovery NMSE depends not only on the sampling rate but also on the shape of the PSD (9), the energy ratio for a fixed sampling rate is affected only by the overall input energy (12). This follows from the fundamental difference between the two objectives of eSampling, i.e., acquisition and energy harvesting: The purpose of acquisition is to allow the complete signal, whose profile depends on the shape of its PSD, to be recovered from its digital representation. However, energy harvesting aims at extracting energy from the signal without having to maintain sufficiency or to avoid distorting the signal, and is invariant of the specific shape of its PSD. The dependency of the energy-fidelity tradeoff on the PSD profile is demonstrated in the following two examples which, unlike Example 2, consider non-purely-bandlimited signals:

Example 3 (Unimodal PSD)

Let be a WSS signal with a PSD given by , where such that . The parameter controls the PSD width, and is set to . The resulting energy-fidelity tradeoff computed via Theorem 2 under the ADC circuit parameters used in Example 2 is depicted in Fig. 6, along with an illustration of the PSD.

[width=0.65]UnimodalPSD.png

Figure 6: NMSE () versus , unimodal PSD.
Example 4 (Multimodal PSD)

Let be a WSS signal with a PSD . Here, is set to . This PSD profile and the energy-fidelity tradeoff evaluated using Theorem 2 under the ADC circuit parameters used in Example 2 is depicted in Fig. 7.

[width=0.65]multimodalPSD.png

Figure 7: NMSE () versus , multimodal PSD.

These examples illustrated in Figs. 6 and 7 demonstrate that eSampling ADCs applied to signals with such spectral profiles can operate with zero power for up to bits of quantization resolution, while achieving approximately ideal reconstruction. Observing Figs. 6-7 and comparing them to Fig. 5, we note that different PSD profiles lead to different energy-fidelity curves. This property is solely due to the dependence of the achievable NMSE on the PSD, which follows from Theorem 1, since both the amount of energy harvested from a stationary signal as well as that consumed in eSampling do not depend on the spectral profile of the signal, but on the sampling rate and the variance .

In particular, the amount of energy harvested (8) when eSampling at is numerically evaluated as pJ, while the corresponding amount of energy consumed (21) when using bit quantizers is pJ. This implies that the eSampling ADC is able to harvest much more energy from the signal than it consumes in converting it into a digital representation, as the energy ratio indicates an energy gain of dB. In particular, it is observed that eSampling ADCs operating with up tp bits per sample are capable of saving power. However, this mode of operation comes at the cost of increased NMSE for higher values of . The examples presented in this subsection indicate that the power consumption of high resolution ADCs can be notably reduced and even mitigated by properly combining acquisition and energy harvesting via eSampling. In Section IV we demonstrate that these results do not follow only from a numerical evaluation of our theoretical results, but also reflect the performance in terms of recovery accuracy and energy efficiency of a dedicated eSampling ADC circuit design.

Iii-E Discussion

Our characterization in the previous subsections focuses on the general family of stationary signals. When the signal obeys some structure, e.g., it is known to be sparse in the frequency domain, ideal recovery can be achieved at low sampling rates using generalized sampling methods

[eldar2015sampling], allowing to harvest more energy without affecting the recovery NMSE. This indicates that the energy-fidelity tradeoff of eSampling ADCs can be further improved by accounting for structured signals, as commonly encountered in communication [cohen2018analog] and radar [cohen2018sub] systems. We leave the analysis of eSampling of structured signals for future work.

The fact that eSampling gives rise to ADCs which operate with zero power and can even harvest more energy than they consume, makes it an attractive technology for low-power systems, such as internet of things devices, sensor networks, as well as wearable and implantable medical units. However, the applicability of the proposed eSampling ADC is limited in some scenarios since its architecture is based on S/H ADCs. For example, S/H ADCs typically operate at sampling rates below GHz, and are not suitable for operating at extremely high sampling rates, where flash ADCs are more commonly used. While we conjecture that the concept of eSampling, namely, the integration of energy harvesting into signal acquisition, can also be combined with alternative ADC technologies other than S/H, we leave this study for future research.

While our analysis focuses on WSS signals for analytical tractability, the proposed eSampling ADCs applies to a much broader family of acquired analog signals. For example the eSampling ADC circuitry detailed in the following section is experimented when acquiring a sinusoidal signal, demonstrating its ability to accurately reconstruct the signal in a power saving manner. Furthermore, our proposed analysis is based on linear recovery, being a common reconstruction framework in sampling theory. In particular, the reconstruction of Nyquist rate sampled bandlimited signals, shift-invariant signals, and various other structures studied in the literature, is based on linear filtering [eldar2015sampling]. However, the architecture of the eSampling ADC is invariant to the reconstruction mechanism, and alternative recovery schemes would result in a different characterization of the energy-fidelity tradeoff.

Iv eSampling ADC Circuit-level Design

In order to demonstrate the hardware feasibility of the concept of eSampling, we present the circuit-level design of such a device. In particular, we design an eSampling ADC circuit based on the model shown in Fig. 2 using standard 65 nm CMOS technology, and carry out its experimental study using a Cadence Virtuoso platform. In order to design the eSampling ADC based on the high-level architecture illustrated in Fig. 2, one has to design its three main sub-blocks: The two-way switch ; the quantizer logic; and the energy harvesting circuit. We thus first elaborate on each of these sub-blocks, after which we present the experimental study.

[width=]switch.pdf

Figure 8: Circuit diagram of (a) PMOS transistor switch, (b) NMOS bootstrapped switch.

Iv-a Two-way switch

The two-way switch allows the input signal to be connected to the hold capacitor during acquisition phase and to the energy harvesting circuit during the hold phase. In our design, is implemented111The term ‘implement’ used here implies the design/simulation of the circuit in Cadence Virtuoso platform, in line with the similar usage of this terminology in [liu201010, 6936944, 8727467, 8676062, 8017456]. using two one-way switches, one for each operation phase, namely, when one switch is open, the other is closed. Each of these switches is realized using a different topology. The switch designed to connect the input signal to the energy harvesting circuit is implemented using a PMOS transistor, as illustrated in Fig. 8(a). The PMOS transistor turns ON when the clock signal is at logic ’0’, indicating that hold phase is active. When is at logic ’1’, it turns OFF and isolates the input signal from the next block. In order to allow both switches of to utilize the same single clock pulse, the switch designed to connect the input signal with the quantizer is implemented using an NMOS transistor, which turns on when is at ’1’.

The on-resistance of a MOS transistor, which determines the value of in (1), is sensitive to fluctuations in the input signal and may vary accordingly [razavi1995principles]. Such variations in may introduce a non-linear distortion at the output of the ADC. To avoid such distortion, we use an NMOS bootstrap switch to connect the input signal to the quantizer, which ensures a constant , as proposed in [7258484]. The design of the NMOS transistor based bootstrapped switch used in this work is illustrated in Fig. 8(b). To achieve nearly constant , the gate of the transistor in Fig. 8(b) is bootstrapped using two PMOS transistors and , three NMOS transistors and , and one capacitor , following [7258484]. Two CMOS inverters and are also employed in the structure to generate the required clock signals needed for proper operation of the switch.

The value of the on-resistance as well as the hold capacitor affect the setting of the acquisition time , as follows from (1). To maximize the amount of energy harvested, small values of are preferable, so that more time could be allocated to harvesting the input signal energy. Reducing requires increasing the width of the transistors [razavi1995principles], which in turn increases the device capacitance, and thus reduces the operating speed of the ADC. In addition, wider devices may result in charge injection [chen1995weak], which degrades the signal-to-noise-distortion ratio (SNDR) of the ADC, and hence the performance of the ADC. Alternatively, employing small values for results in mismatch issues and sampling noise, which degrade the ADC conversion accuracy [7890, chen2014capacitor]. These drawbacks require the acquisition time to be large enough such that the ADC performance is not compromised, and is in fact the primary reason S/H ADCs are typically limited to operate with sampling rates below 1 GHz, as discussed in Subsection III-E.

Iv-B Quantizer

The dedicated eSampling ADC circuit design is based on S/H SAR ADC architectures [6341363, 6043594, hariprasath2010merged] as illustrated in Figs. 1-2. Such quantizers generally consist of a DAC, a voltage comparator and a SAR logic, which map the voltage of the hold capacitor (also known as the total capacitance of DAC array) into an -bit value by successively refining the digital representation using a binary search algorithm. In our eSampling ADC circuit we use a single-ended merge capacitor switching (MCS) based SAR ADC. For such devices, the total capacitance of the DAC array is , where is the unit capacitance of the DAC array, as illustrated in Fig. 9.

[width=0.65]Capacitive_DAC_array.pdf

Figure 9: DAC capacitor array schematic diagram.

In particular, during acquisition phase the input signal is connected to the top plate of the DAC capacitor array, while the bottom plate is connected to the common mode voltage, i.e., . Once the acquisition phase is over, the voltage at the top plate of the DAC capacitor array is reduced by common mode voltage, and hence equals to . The top plate of the DAC capacitor array is connected to the positive terminal of the comparator, while the negative terminal of the comparator is grounded. The comparator then compares the voltage of its positive terminal with its negative terminal. If the voltage at the positive terminal is higher than the negative terminal, the comparator yields an output of logic ‘1’, else logic ‘0’. The output of the comparator is passed to the SAR logic, which resolves the most significant bit (MSB). The decision on the MSB is fed back to the DAC and the bottom plate of the largest capacitor of DAC capacitor array is switched from to ground (if MSB=1) or (if MSB=0). This operation changes the voltage at the top plate of the DAC capacitor array, and a new decision is made by the comparator, which is sent to the SAR logic to resolve the second MSB and so on. The process continues for all bits. The overall resistance of the switches is determined by the binary scale switch resistance, , as illustrated in Fig. 9.

As discussed in Subsection II-A, the energy consumption of S/H SAR ADCs is effectively dictated by its quantization sub-blocks. Therefore in the following, we detail the circuitry used for the quantizer along with its energy usage per sample.

The voltage comparator is implemented using a dynamic latch. The energy consumed per sample of a dynamic latch comparator is given by [6043594]

(18)

where , is the capacitive load of the comparator, is the gain during regenerative phase, and is the ratio of the drain current of the device with its trans-conductance [4588351]. The SAR logic is realized using two arrays of shift registers that operate in serial-in-parallel-out and parallel-in-parallel-out modes [5771068]. Each register is implemented using a D flip-flop circuit, and the resulting energy consumption is given by [6043594]

(19)

where is the input capacitance of the D flip-flop, and is the total activity parameter of the SAR logic. Finally, the DAC is based on a binary-weighted capacitive DAC, designed using the MCS scheme [hariprasath2010merged]. The energy consumption of the MCS DAC is given by [hariprasath2010merged]

(20)

where .

To summarize, the total energy consumption during hold phase of our dedicated eSampling ADC circuit design, which dictates the overall energy consumed per sample, is given by

(21)

where follows from (18), (19), and (20). The energy term in (21) obeys the second-order polynomial model of (4), used in our analysis of eSampling ADCs in Section III.

Iv-C Energy Harvesting Circuit

The proposed eSampling ADC harvests the input signal energy during hold phase and stores this energy in a capacitor, . As detailed in Subsection II-B, energy harvesting circuits typically consist of a capacitor, in which the harvested energy is stored, and a signal conditioning circuit, whose purpose is to facilitate the charging of the capacitor. In our design, we do not include a signal conditioning circuit and forward the input signal directly to during hold time. This simplified design is sufficient for our experimental purposes, where we use synthetic controlled input signals with strictly positive voltage values. However, in order to achieve efficient energy harvesting of a low voltage complex rapidly alternating signals, one should also include signal conditioning devices, such as a rectifier, voltage regulator, and DC-DC converter.

To quantify the maximum amount of energy that can be harvested in an analytically tractable manner, we consider the case where the input signal is approximately constant during the hold phase, i.e., for each . The purpose of this approximation is to facilitate characterizing the amount of energy harvested in a tractable manner. In addition, we focus on the scenario in which the capacitor is empty at the beginning at the hold phase, namely, the voltage on the capacitor , denoted , satisfies . In this setup, the capacitor voltage at the end of the hold phase, i.e., at time instance , is given by

(22)

where, as defined in Subsection III-A, is the resistance of the energy harvesting circuit. This resistance is dictated here by the on-resistance of the PMOS transistor in the two-way switch. The amount of energy harvested in such a sampling interval is given by

(23)

where follows from (22), and stems from the fact that the input is approximately constant during the hold phase. Comparing (23) and (8) reveals that the efficiency of this simple energy harvesting circuit can be approximated as

(24)

The expression for the energy harvesting efficiency in (24) can be used to provide guidelines for determining the capacitance used in the circuit. In particular, it can be shown that (24) is maximized when . However, the derivation of (24) is carried out assuming that the capacitor is empty at the beginning of the hold phase. This implies that its stored energy is transferred to some external storage device, e.g., battery, after each sample. In practice, energy transfer typically takes much longer than a single sampling interval, and thus it is preferable to carry out such a transfer only once every multiple samples. This is achieved by using a capacitor with a larger value of , which allows to store more energy and provides a nearly constant voltage at the load, but requires more time to charge. In particular, in our experimental setup detailed in Subsection IV-D, we set , which results in the capacitor taking approximately samples to charge up. Under such a setting, the period dedicated to transferring its energy once it is fully charged, during which energy harvesting is inactive, has only a minor effect on the overall harvested energy.

Iv-D Experimental study

To validate that the energy saving potential of eSampling ADC observed in Section III also reflects its behavior in a real world environment, we next evaluate the eSampler circuit design. To that aim, a schematic of the eSampling ADC circuit has been created in Cadence Virtuoso platform based on the circuit-level design detailed in the previous subsections. The proposed eSampling ADC operates at a sampling frequency of MHz with an bit quantizer. For our experimental purpose, we use a sinusoidal signal, being a common benchmark for evaluating the accuracy of ADC circuits [kester2005data, Ch. 2]. The maximum frequency of the input signal is MHz, thus the sampling rate satisfies the Nyquist condition. The amplitude of the signal varies from 0 to . Here, we use an energy harvesting capacitor of nF, while the remaining parameters are the same those detailed in Examples 2-4.

We first assert that the eSampling ADC is indeed capable of accurately reconstructing the signal sampled at the Nyquist rate. To that aim, we depict the fast Fourier transform (FFT) of the reconstructed signal, computed using a 1024-point FFT, in Fig. 10. As expected, the FFT noise floor is determined by the SNDR due to quantization, computed by the dB rule of thumb as approximately dB, with the additional FFT processing gain of dB [kester2005data, Ch. 2]. In particular, the gap between the noise floor observed in Fig. 10 and the energy of the signal at its central frequency of MHz, is roughly dB, settling with the theoretical performance of ADCs satisfying Nyquist condition, and indicating that the designed eSampling ADC accurately reconstructs the observed analog signal.

[width=0.65height=2.7in]ffthf.pdf

Figure 10: FFT plot of reconstructed signal for 8 bit eSampling ADC.

Next, we focus on the energy harvesting circuit of the designed eSampler, in order to identify how many sampling rounds are required for the capacitor to charge up. To that aim, we plot in Fig. 11 the voltage on the energy harvesting capacitor over time. Observing Fig. 11, we note that for the given input signal, the capacitor reaches a steady level of mV after s, which correspond to samples at MHz. Based on Fig. 11, we design the eSampling ADC to transfer the energy stored in its energy harvesting capacitor once every samples. We dedicate approximately s for each transfer, during which the energy harvesting circuit is inactive, resulting in each cycle of harvesting and transferring taking approximately samples. Consequently, the effective amount of energy harvested per sample of the eSampling ADC is given by

(25)

[width=0.65height=2.7in]Veh_final.pdf

Figure 11: Voltage obtained across for 8 bit eSampling ADC.

The amount of energy harvested per sample, evaluated in (25) based on the experiment in Fig. 11, does not represent the overall energy balance of the eSampling ADC, as it accounts only for the amount of energy harvested. Therefore, to demonstrate that the eSampling ADC circuit design not only accurately recovers the signal and harvests energy, but also saves more energy than it consumes, we next evaluate both the energy harvested and the energy consumed by the ADC circuit. The average energy consumption of our designed circuit is computed by evaluating the current drawn from its reference source , denoted , and thus the energy consumed at each time instance can be obtained by

(26)

The resulting growth of both the energy consumed and the energy harvested are depicted in Fig. 12. Observing Fig. 12, we note that the eSampling ADC harvests much more energy than it consumes, while still being able to accurately reconstruct its input signal as demonstrated in Fig. 10. In particular, the consumed energy is shown to grow in an approximately linear manner, with an average energy consumption of pJ per sample. The maximal amount of energy which can be obtained is dictated by the external battery, to which the harvested power is periodically transferred. Comparing this to (25) reveals that the true energy ratio of the eSampling ADC, which periodically transfers its harvested energy to an external battery, is approximately dB, which is within a relatively small gap from the theoretical results observed in Subsection III-D. This gap can be further reduced by using more advanced energy harvesting circuitry, compared to the simplistic design detailed in Subsection IV-C. In particular, using more advanced harvesting architecture can increase the efficiency , allowing to achieve improved energy-fidelity tradeoffs compared to those observed here. Nonetheless, despite its relatively simple architecture, the eSampling ADC circuit design is still shown to be able to achieve accurate reconstruction while harvesting substantially more energy than it consumes.

[width=0.65height=2.7in]Energy_harvested_vs_consumed_practical.pdf

Figure 12: Total energy harvested and energy consumed versus time for an 8 bit eSampling ADC.

V Conclusion

In this paper, we proposed the eSampling ADC architecture, which modifies the traditional conversion process of a S/H ADC to harvest energy from the discarded portion of the input signal. We analyzed the amount of energy which can be harvested from stationary signals and characterized the underlying fundamental tradeoff between energy harvested and reconstruction fidelity which arises from the joint acquisition and energy harvesting paradigm. Our theoretic characterization reveals that an eSampling ADC with up to 12 bits can harvest more power than it consumes, when sampling both bandlimited signals and non-bandlimited ones at a sampling rate allowing recovery with negligible error. Then, we presented a circuit-level design of an eSampling ADC using CMOS 65 nm technology demonstrating the feasibility of this concept. Our experimental results validated the theoretical observations, showing that an eSampling 8-bit ADC circuit applied to a sinusoidal signal harvests more power than it consumes while recovering the analog signal in a nearly perfect manner.

References