Deep neural networks (DNNs) have been widely applied to solve various practical problems with state-of-the-art performance. Recurrent neural networks (RNNs) which are a subset architecture of DNNs, are particularly useful in applications involving time series inputs, such as speech recognition [1, 2] and dynamical system control[3, 4]
. In contrast to Convolutional Neural Networks (CNN
s) which use filter kernels, RNNs are fully-connected networks: They take a 1D vector as input and produce a vector of output. The feature vectors generated by CNNs can be fed into an RNN for further processing. In this way, RNNs can connect the high dimensional input features over time, which is useful for complex sequential classification or regression tasks. Gated RNNs modify a “vanilla” RNN to add nonlinear operations to the units that allow them to memorize and gate their output. Long Short-Term Memory units (LSTM)  and Gated-Recurrent Units (GRU) BPTT), where the sequential operations of the RNN are unrolled to compute the weight updates based on output error. By using BPTT with labeled training data, GRU and LSTM RNNs can be trained to high accuracy for tasks involving time series such as continuous speech recognition.
Edge computing devices that embed some intelligence implemented through trained DNNs are gaining interest in recent years. An advantage of edge computing is that computations are done locally on end-user devices to reduce latency and protect privacy . Most literature reports on the use of CNNs for edge devices. There is less reported on devices that use RNNs particularly on embedded low-latency, high energy-efficient platforms that use FPGAs. RNNs also have larger memory footprints and memory access of the fully-connected weight matrices dominates power consumption. RNNs are usually computed on the cloud which introduces large and variable latency, thereby making it hard to guarantee real-time performance for edge applications such as human-computer interaction devices and mobile, robotic applications.
Optimization methods have been applied to RNNs for embedded hardware implementations (e.g. weight pruning in ESE , and structure pruning in BBS ). We also previously reported the DeltaRNN accelerator  that uses the delta network algorithm . Our first DeltaRNN implementation  stored the large weight matrices in FPGA block RAM and thus needed expensive FPGA boards with greater than 15 W power consumption. However, this work only focused on pushing the limit of high batch-1 throughput without considering the memory and power constraints of extreme edge devices. Typical chips for edge applications, such as microcontrollers and small-footprint FPGA, only have a few hundreds of kilobytes (kB) of on-chip SRAM, but large RNNs usually have megabytes (MB) of parameters, making them difficult to be buffered on-chip even after compression. In this case, storing RNN parameters in off-chip memory such as flash or DDR memory is an inevitable choice for edge devices. Therefore, reported hardware RNN implementations [9, 10] cannot be easily scaled down for edge platforms.
This work is on EdgeDRNN, a hardware accelerator for RNN computation on the edge . Because of our interest in real-time edge applications, our focus is on supporting low-latency batch-1 inference of large RNNs for real-time performance on low-cost and low power but very constrained edge platforms. We show that our implementation can run large-scale multi-layer RNNs using a small number of processing elements with the large weight matrices stored on off-chip DRAM. Besides accelerating RNN inference, it leaves most cycles of the CPU in the system-on-chip (SoC
) available for other tasks, such as feature extraction and I/O management. EdgeDRNN can be implemented on a small-footprint FPGA with 19X less logic cells and 15X less on-chip memory compared to the one used in DeltaRNN. Thus, EdgeDRNN is suitable for embedded system applications such as robotics (Fig. 1B).
Moreover, in previous work using the current delta network algorithm, a global threshold is applied on both the inputs and hidden unit activations of every layer of the network in sparsifying the activation vector. In this work, we looked at how different threshold values on the inputs and activations of hidden units affect the trade-off between the accuracy of the network on a regression task and the sparsity levels of the change in the activation vectors. A higher sparsity level implies reduced weight memory access and reduced computes.
This paper makes the following contributions:
We describe a flexible, low-cost, high throughput edge FPGA RNN accelerator that uses a spiking neural network-inspired Delta RNN principle to provide state-of-art latency and power efficiency for a wide range of gated RNN network sizes with batch size of 1.
We report the first study of a delta network that uses different delta thresholds for the input and activations of the hidden units. On our tested regression task, this modification increases temporal sparsity of hidden delta states by 16% compared to using a global threshold.
We compare the usability and throughput performance of two different EdgeDRNN implementation on the SoC FPGA: Bare-metal and embedded Linux. The latter enables faster development and we report the correct FPGA memory bus port configuration that minimizes the performance loss due to CPU contention for the memory controller.
We report benchmark latency and throughput numbers of RNN inference on state-of-the-art commercial chips for edge applications. To our best knowledge, these numbers have never been reported before.
The rest of this paper is organized as follows. Section II describes the background of gated recurrent unit (GRU) based RNN and the algorithm of delta network based GRU-RNN, which is called DeltaGRU. Section III describes the architectural design of the accelerator and its implementation on MiniZed. Section IV discusses experimental results including the experiments using different delta thresholds for the network. Section V compares the proposed accelerator with prior work and commercial edge devices. Section VI concludes the paper.
Ii-a DNN hardware optimization methods:
Various methods have been proposed to reduce the dominant RNN matrix-vector (MxV) operations. Static approximation methods (i.e. constructed during training) include quantization, arithmetic, and weight pruning.
Quantization: Quantizing floating-point weights or activations to fixed-point numbers with shorter bit width reduces memory footprint of networks and make it possible to use fixed-point MAC units instead of expensive floating-point MAC units [14, 15, 16, 9]. Chip area can be further reduced by replacing conventional fixed-point multipliers by look-up table based  or multiplexer  based multipliers on low bit precision networks with 2-4 bit weights. By including quantization during training (e.g. by using an approach like dual-copy rounding ) it is possible to reduce weight precision to 8 bits without accuracy loss.
Pruning removes unimportant neuron connections that results in sparse weight matrices. Sparse matrices can be encoded into a sparse matrix format such as the Compressed Sparse Column (CSC) and Compressed Sparse Row (CSR). With an accelerator that can decode the sparse matrix format on-chip, the sparse matrix-vector (SpMV) multiplication can be accelerated by executing multiply-and-accumulate (MAC) operations only on nonzero weights. This approach was adopted by the Efficient Speech Recognition Engine (ESE) . Because unstructured pruning results in computation that is hard to balance across processing elements, structured pruning methods have also been proposed to improve load balancing during the SpMV computation [10, 21]. This approach was used by the LSTM FPGA accelerator using Bank Balanced Sparsity (BBS) . It is also used by the custom digital IC of  where it is called Hierarchical Coarse Grain Sparsity (HCGS). Structured pruning is a popular approach for improving RNN hardware performance; both BBS and HCGS use it to increase effective MAC efficiency, but large increases in efficiency result in significantly worse inference accuracy 
. For example, a 16X compression increases the error rate by a factor of about 1.2X. It allows static (compile-time) optimization, but training is fairly complicated since exploration of the additional structure hyperparameter values is needed to find optimum values that are matched to the particular hardware.
Arithmetic: Bit-serial NN accelerators such as [22, 23] utilize a flexible bit-serial MAC to support various precision of network parameters and are smaller in area compared to conventional fixed-point MAC units. However, since a bit-serial MAC units requires more cycles to finish a multiplication between high bit precision operands, more bit-serial MAC units are required to achieve higher throughput than using conventional MAC units and larger adder trees are need for accumulating partial sums. Thus, the average speedup using this method is only around 2X but it comes with extra overhead area. The C-LSTM accelerator used Toeplitz-like weight matrices in the form of blocked circulant matrices to reduce RNN memory requirements 
since multiple rows in each circulant matrix block can be generated from a single vector. The method also enables the use of Fast Fourier Transform (FFT) to reduce the MxV cost from to . However, forcing weight matrices to be blocked circulant is coarse-grained and leads to higher accuracy degradation compared to weight pruning [9, 10]. Moreover, the method leads to hardware overhead of computing the FFTs of activations and weights.
Temporal sparsity: The delta network algorithm  capitalizes on the temporal sparsity of activation state vectors in a network. Setting a finite threshold that is greater than zero has the effect of zeroing-out below-threshold elements of the activation vector, which results in sparse delta vectors. Since zero activations have no downstream influence, these MACs can be skipped. It means that entire columns of the weight matrix can be skipped. Thus delta networks marry the temporal sparsity of spiking networks with the synchronous update and analog state transmission of conventional deep networks. Combining these principles provides the benefits of sparse computing and efficient communication of precise analog information with reduced and predictable memory access of inexpensive DRAM which is crucial for storing the weights.
A set of studies [12, 13, 7] showed in a variety of networks that by applying the delta principle during training, the accuracy loss is minimal even with a 5-10X improvement of RNN throughput and latency. For example,  used a 4-layer 320 units per layer GRU RNN for continuous speech recognition on the Wall Street Journal dataset. The Word Error Rate (WER) increased by only a factor of 1.08X but with a reduced memory access of 6.2X.
Ii-B Gated Recurrent Unit
The update equations for a GRU layer of neurons and -dimensional input, which are as follows:
where are the reset gate, the update gate and the cell state respectively. , are weight matrices and
are bias vectors. The
variable denotes the logistic sigmoid function. Each GRU input is the vectorand its output is the vector .
Fig. 2A illustrates the update of the normal GRU reset gate as a flow diagram.
The delta network method is applied to the GRU-RNN architecture; we call this DeltaGRU. Assume an input vector sequence with sequence length of , we first declare the following variables:
where is the -th element of input state memory vectors in timestep . is the -th element of hidden state memory vectors in timestep . is the -th element of delta input state vectors . is the -th element of delta hidden state vectors . and are respectively the delta thresholds of inputs and hidden state for each layer. In the initial timestep (), , , are all initialized to zeros.
The update equations for the DeltaGRU are now:
where , , , are delta memory vectors and . Variables and indicate the sigmoid function and element-wise multiplication of vectors respectively.
Fig. 2B illustrates these operations for the DeltaGRU reset gate. The input vector and the hidden state vector are respectively replaced by the delta input state vector and the delta hidden state vector . Values of the previous state memory vectors , are updated using Eq. 2 to generate new state memory vectors , . The previous delta memory vector holds the previous step’s partial sum-product and the resulting new delta memory vector is stored. Otherwise the operations are the same as for the original GRU reset gate, as shown in Fig. 2A. The other gates have similar flow diagrams. The state and delta memories are 1D vectors and can be easily fit into on-chip SRAM buffers.
Ii-D Temporal Sparsity
The temporal sparsity of a DeltaGRU network of layers with an input sequence length of is defined as the fraction of zeros in the and vectors, signified by and respectively. The effective temporal sparsity is the weighted average of and according to the number of network parameters they correspond to. The definition of temporal sparsity is given by Eq. 4:
where and are the number of zero elements respectively in the delta vectors and in layer at timestep . Because operations on biases are negligible, they are ignored in Eq. 4.
By skipping zero elements in delta vectors, whole columns of matrix-vector MAC operations can be skipped. If the delta network is properly trained (by including the delta operation), [12, 7, 26] showed that the number of operations can be reduced by 5X to 100X with negligible loss of accuracy, depending on the temporal evolution of the states of the input and hidden units.
Two datasets are used in this paper: the TIDIGITS  dataset for the classification task and the SensorsGas dataset for the regression task. The TIDIGITS speech dataset has more than 25k digit sequences spoken by over 300 men, women, and children. The entire training and test sets are used in our experiments. The SensorsGas dataset consists of recordings of metal-oxide sensors in response to various concentrations of carbon monoxide gas over 14 days [28, 29]. This dataset was used in  to evaluate the network performance of a gated RNN in predicting the concentration of carbon monoxide. The dataset used here comes from the 70/30 Split variant, that is, 70% of the sequences are randomly selected to form the training set, while the remaining sequences form the test set.
Iii EdgeDRNN Accelerator
Due to limited weight reuse, it is difficult to compute RNNs efficiently for real-time applications that usually work best with a batch size of 1. Therefore, a big challenge of RNN inference on the edge is the scarce off-chip memory bandwidth available on portable platforms, and the limited amount of on-chip block RAM on small FPGAs. EdgeDRNN uses cheap off-chip DRAM for weight storage and reduces memory bandwidth by exploiting temporal sparsity in RNN updates.
Fig. 3 shows the architecture of the EdgeDRNN accelerator. The main modules consist of the Delta Unit for encoding delta vectors and generating weight column pointers (pcol); the Processing Element (PE) Array for matrix-sparse vector multiplications; the (CTRL) control module which contains finite state machines (FSMs) and encodes instructions to control the AXI Datamover. Other modules include the configuration module (CFG) composed of configuration registers; the output buffer (OBUF) for buffering and redirecting outputs back to the Delta Unit and the W-FIFO for buffering weights.
Iii-B Delta Unit & CTRL
The Delta Unit stores state memory for delta state vector encoding in a block random access memory (BRAM111BRAM is the standard SRAM memory block on FPGAs; on Xilinx Zynq FPGAs a single BRAM block has 18-bit words and a capacity of 18kb). The FSM addresses the BRAM according to the valid signal of input state vectors and , one of which, is selected to be processed as at a time depending on the FSM state. The Delta Unit encodes one element of a delta state vector in each clock cycle after the valid signal asserted until the whole vector is processed.
The vector sizes are provided by the config signal from the CFG module. Delta state vector elements that are greater than or equal to threshold or ; and their corresponding physical weight column address pointer (pcol) are respectively dispatched to the D-FIFO and CTRL. The corresponding state element is written into the BRAM to update the state memory. Otherwise, elements are discarded without being written into the D-FIFO. By using only Delta unit, the latency in clock cycles for the Delta Unit to process a vector is exactly the length of that vector. It is possible to reduce the latency by searching for nonzero elements in subsections of a vector simultaneously. It can be realized by using
Delta Unit blocks in parallel to fill at most one nonzero value into the D-FIFO on every clock cycle. Assuming that nonzero elements are uniformly distributed in a delta state vector and usingDelta Unit blocks running in parallel, the latency in clock cycles to process a whole vector is
where is the length of the vector, is the length of the subsection of the vector or the look-ahead window side of the Delta Unit; and is the temporal sparsity defined in Eq. 4.
Although can be hidden under , the latency of computing MxV, becomes a bottleneck of total latency when , which could happen when an accelerator uses a large number of MAC units to compute small networks. However, in this work, we aim to run large network inference with a small number of MAC units for edge applications, making ; thus, is used in EdgeDRNN. The MAC utilization results shown in Section IV.D prove that this choice did not lead to latency bottleneck.
The CTRL module contains FSMs that control the PE array. This module generates 80-bit instructions for controlling the Xilinx AXI Datamover IP  to fetch RNN parameters. The instruction contains pcol and the burst length calculated from the dimensions of the network stored in configuration registers.
Iii-C Processing Element Array
Two-dimensional arithmetic unit arrays such as systolic arrays are difficult to be fully utilized in portable edge devices due to scarce on-chip memory resources, the low external memory bandwidth of the system and the limited weight reuse nature of RNNs. In order to fully utilize every PE, a vector PE array is used in EdgeDRNN. Fig. 5 show the internal structure of a PE.
The PE has a 16-bit multiplier MUL and two adders, 32-bit ADD0 and 16-bit ADD1. Multiplexers are placed before operands of MUL so that the PE can be reused for both MxV and vector dot products. The multiplexer below ADD0 selects between ’0’ and the BRAM data. ’0’ is chosen when an initialization of BRAM is needed as shown in Fig. 5. ADD1 is responsible for element-wise vector additions. All units are parameterized in the System Verilog RTL and configurable at compile-time to support any fixed-point precision within their designed bit width. The PE supports tanh and sigmoid functions by using look-up tables (LUTs). The input bit width of LUTs is fixed to 16 bits while the output bit width can be set anywhere between 5 (Q1.4) to 9 (Q1.8) bits.
Fig. 6 shows the sparse MxV flow. The weight matrices of the GRU-RNN are concatenated following the arrangement shown on the right half of the figure. Biases are appended to the concatenated weight matrix as the first column and an element is appended to each input state vector as the first element. The PE array multiplies only nonzero delta state elements with corresponding valid columns. Products are accumulated in the Accumulation Memory (ACC Mem) to compute delta memory vectors , , , . Products involving , , are accumulated to ; , , to ; , to ; to . According to the delta update scheme defined by Eq. 2, the appended in the delta state vector becomes after the initial timestep, which means that biases , , are only accumulated to the ACC Mem by once and will be skipped by the Delta Unit after the initial timestep.
The calculation of activation after the MxV is also done by the PE array and stages of this process are shown in Fig. 7. The PE array fetches the delta memory vectors from the ACC Mem to calculate in 8 pipeline stages. Paths without any operator in any stage are buffered for 1 clock cycle using flip-flops. During execution of the activation generation, stages S0S2 are executed simultaneously with S5S7 to reuse the arithmetic units using time-division multiplexing.
Finally, assuming that the DRAM interface can deliver bits per RNN clock cycle for weight fetch, the optimum number of PEs in the array is determined by the weight precision bit width . The definition of and corresponding theoretical peak throughput, , is defined below:
where is the clock frequency of the programmable logic. For example, the FPGA used in this paper has a 64-bit DRAM interface, so, with 16-bit weights, is optimal.
Iii-D Implementation on MiniZed
Fig. 8 shows the latest implementation of EdgeDRNN on the $89 MiniZed development board  which has a Zynq-7007S SoC. EdgeDRNN is implemented in the programmable logic (PL). The SoC also has a programmable CPU which is in a module called the Processing System (PS). Data is transferred between PS and PL through high performance (HP) slave ports while control signals generated by the PS is transferred through general purpose (GP) master ports. The hard IP block, AXI Datamover, is controlled by the PS to fetch weights to the PL from DDR3L memory. Another hard IP block, AXI DMA is controlled by the PS to transfer inputs and outputs of the accelerator. Compared to our previous work , we reduced resource utilization by replacing the AXI SmartConnect IP with the AXI Interconnect IP while preserving the same throughput and latency. To further reduce on-chip power, we used the power optimization strategy during implementation in Xilinx Vivado and lower the ARM CPU clock frequency from 667 MHz to 400 MHz for the bare-metal version.
The peak DRAM read memory bandwidth is 1 GB/s at the 125 MHz clock frequency (64-bits125 MHz/8-bits/byte). EdgeDRNN can be configured to support 1, 2, 4, 8, 16-bit fixed-point weights and 16-bit fixed-point activations. In this paper, EdgeDRNN is configured to support 16-bit activation and 8-bit weights. To fully exploit this HP port bandwidth, we implement PEs following Eq. 6. Adding more PEs would only leave them idle since weight fetches are limited by the DRAM bandwidth.
The AXI-Lite General Purpose (GP) master port is used for the single-core ARM Cortex-A9 CPU to control the AXI-DMA and to write the configuration to the accelerator. Configurations include physical start address of the concatenated weights, delta thresholds, and network dimensions.
The PL is driven by single clock domain of 125 MHz generated by the PS. Table I shows the resource utilization solely for EdgeDRNN (with 5-bit (Q1.4) LUTs) and for the whole PL after synthesis and implementation. BRAMs are used to store previous state memory in the Delta Units and the accumulation memory in PEs and FIFOs. 8 DSPs are used for the MAC units in the 8 PEs while the remaining DSP in CTRL produces weight column addresses. The most consumed resources are LUTs (72%). This entry-level XC7Z007S FPGA has only 14.4k LUTs. By comparison, the top level XC7Z100 has 19X more LUTs and 11X more BRAM.
Iii-E Petalinux OS Integration
Xilinx’s Zynq chips are hosted on heterogeneous embedded platforms with a variety of peripherals and communication interfaces. To work with this type of system there are two workflows, bare-metal and embedded OS.
The bare-metal workflow is similar to the workflow of conventional microcontrollers. Bare-metal has a set of libraries that establish a very thin software layer over all the hardware resources available in the system and that helps a little during the elaboration of the software that will be deployed in the system; however, detailed knowledge of the hardware is still necessary to ensure correct functionality. The resulting software runs on the PS processor making use of all its computing power since it is the only software running on the core. Bare-metal allows a more dedicated use of the system resources to achieve high performance execution but it offers little flexibility and versatility.
The second option is to use an embedded Linux OS provided by Xilinx called PetaLinux. This OS establishes several software layers over the system hardware that simplifies its use and the development of applications that make use of the system’s peripherals like USB, Bluetooth, and Wi-Fi. The Linux system is a preemptive multitasking operating system that can make application development much faster. Since running Linux slightly slows down inference (Sec. IV), users can decide to pay the throughput price of using Linux for faster development time and easier maintenance. For EdgeDRNN, we implemented both systems to meet our various application requirements.
Iv Experimental Results
. Here we report the results of new experiments to measure accuracy, throughput, and power efficiency on the spoken digit task and a new regression task on gas concentration estimation. We also report measurements of embedded Linux implementation of EdgeDRNN.
Iv-a Experimental Setup: Training
We evaluate the accuracy of DeltaGRU and the hardware performance of EdgeDRNN using this DeltaGRU network on both a classification task using the TIDIGITS  dataset and on a regression task using the SensorsGas  dataset.
For the classification task, we trained 6 different DeltaGRU network sizes and compared their WER on the TIDIGITS
audio digit dataset, evaluated using the greedy decoder. Inputs to the networks consist of 40-dimensional log filter bank features extracted from audio sampled at 20 kHz using a frame size of 25 ms and frame stride of 10 ms. We use the Connectionist Temporal Classification (CTC) loss 
to handle variable input sequence lengths. The DeltaGRU networks were trained for 50 epochs using a learning rate of 3e-4 and batch size of 32. Following a similar procedure in, a continuous spoken digit recognition demo is built using EdgeDRNN to prove the system functionality222https://www.youtube.com/watch?v=XyN-jh5yiMI.
For the SensorsGas regression task, the input dimension of the network is 14 corresponding to data from the 14 sensors. We adopt a 2-step pretrain and retrain scheme we developed for : 1) We pretrain a cuDNN GRU model on the training set for 100 epochs. The learning rate is 5e-4 and the batch size of 64. 2) We load these parameters into a DeltaGRU network with same size as the cuDNN GRU and retrain for another 10 epochs with learning rate of 3e-3 and batch size of 256. In this step we optimize the deltas for the visible and hidden units. Because the cuDNN GRU model is highly optimized for NVIDIA GPUs, the pretrain step helps to train the network to achieve high accuracy with 5X less time.
All networks are trained using the Adam optimizer and quantization-aware training using quantization scheme similar to 
. To improve accuracy, we use nonlinear functions with the same input and output bit precision as the LUT in the forward phase of the training. In the backward phase, the gradient of the nonlinear function is calculated using the original nonlinear functions in FP32 precision. Training was done with PyTorch 1.2.0 on NVIDIA GPUs running CUDA 10 and cuDNN 7.6.
Iv-B Experimental Setup: Network Implementation
After the quantized DeltaGRU is trained for a particular task, a Python script converts the PyTorch network modules into C/C++ hardware network header files. These files contain the network parameters and configuration register values for EdgeDRNN. By including the header files, bare-metal or PetaLinux applications are compiled using the standard cross compiler. The resulting system image is transferred to the QSPI flash (bare-metal) or eMMC storage (PetaLinux) on the MiniZed. In each timestep of the RNN, a feature vector is transferred from the PS to the accelerator using the AXI DMA. For measuring the performance of the accelerator, features are calculated offline on a computer and stored in a header file. For using the accelerator in real-world applications, features such as log filter bank and spike count features for audio, are calculated online by the ARM core in the PS. A flag connected to a PS hardware register is raised at the end of each timestep.
Iv-C Accuracy & Throughput
Fig. 9 shows the EdgeDRNN throughput and WER on the TIDIGITS test set versus the used in training and testing of a 2L-768H-DeltaGRU network. is the same for both and . With PEs and PL frequency MHz, EdgeDRNN has a theoretical peak throughput of GOp/s. At , there is still a speedup of about 2X from natural sparsity of the delta vectors. Higher leads to better effective throughput, but with gradually increasing WER. The optimal point is at (0.25), just before a dramatic increase of WER, where EdgeDRNN achieves an effective throughput around 20.2 GOp/s with 1.3% WER. WER and throughput of smaller tested networks are shown in Table II. The 5-bit (Q1.4) LUT was used for this task and did not lead to accuracy loss compared to the network running on CPU with FP32 nonlinear functions.
|Latency (s)||Eff. Throughput (GOp/s)||
|Latency (s)||Eff. Throughput (GOp/s)||
In this regression task, we evaluate the impact of using different delta thresholds for and on the accuracy results of a 2L-256H-DeltaGRU model evaluated on the SensorsGas testset. Fig. 10 and Fig. 11 show respectively the regression accuracy and temporal sparsity versus and . The pretrained 2L-256H-GRU network without using a delta threshold, achieves a root-mean-square error (RMSE) of 0.995 and coefficient of determination () of 0.976. This accuracy was achieved using 5-bit (Q1.4) LUTs, which gave the lowest RMSE out of all other LUT bit precision values.
Similar to the results for the classification task, Fig. 10 shows that the accuracy degrades when larger delta thresholds are used. Fig. 11 shows that the sparsity levels of and are heavily influenced by their corresponding delta thresholds. The accuracy degrades faster with increasing for a fixed than with increasing for a fixed . has a minor impact on and vice versa. The results from this regression task indicate that propagating changes more often in input states is more important than propagating changes in hidden states. By exploiting this phenomenon, we get the optimal point , where the RMSE and are 1.078 and 0.972 respectively. With and , the latency of the optimal model is 206 s. In comparison, Jetson TX2 runs a 4.8X smaller 1L-200H-GRU network in 271 s .
Iv-D Theoretical & Measured Performance
Eq. 7 gives the estimated mean effective throughput of EdgeDRNN running a DeltaGRU layer:
where is the number of operations in a DeltaGRU layer per timestep, the latency of MxV, the latency of remaining operations to produce the activation, and the other variables are defined as in Eqs. 4 and 6.
Table II compares the Eq. 7 predictions with benchmark results of different DeltaGRU network sizes running on EdgeDRNN. Estimated results calculated from Eq. 7 are close to measured results and the maximum relative error between them is smaller than 7.1%. Thus Eq. 7 can be used to estimate EdgeDRNN performance for a particular RNN network size. On average, EdgeDRNN can run all tested networks under 0.54 ms latency corresponding to 20.2 GOp/s effective throughput for the 2L-768H-DeltaGRU.
Iv-E Performance in PetaLinux
For performance measurements on the PetaLinux-based system, we implemented an application that performs the same operations as the software implemented for bare-metal but use the AXI DMA driver included in the OS.
Table III shows the latency and performance results for the 6 networks used in this work. The minimum and mean latency numbers in the PetaLinux version are respectively up to 3.4% and 11.3% higher than the numbers obtained for the bare-metal version. Because the minimum PetaLinux latency is nearly the same as the bare-metal latency, the big difference in maximum latency numbers between the PetaLinux and the bare-metal version is due to CPU contention for other tasks running on the PS that lock the single PS DDR controller. EdgeDRNN fetches weights from HP ports (Fig. 8) that are routed through the PS DDR controller. (The FPGA’s ACP interface should not be used to access DRAM memory under PetaLinux because it is connected directly to the L2 cache on the ARM core where the OS runs. This configuration creates conflicts and the performance of the system is seriously compromised.) Under PetaLinux, the HP interface should be used to connect any module placed on the PL that requires direct access to the DRAM memory.
To understand the impact of CPU load and CPU DRAM access on the RNN inference time, we wrote a small program that loops over a memory array and is designed to trigger L2 cache misses. We used two different memory array sizes to study the effect of cache misses since the large memory array causes more L2 cache misses. Table IV shows that the impact on RNN latency is minor: a small network takes about 50% longer to run with either memory array size, and a large RNN is only slowed down by 10%.
|Mean Latency (us)|
|1L-256H-TH64 (little network with few parameters)|
|EdgeDRNN + Small memory workload||72|
|EdgeDRNN + Large memory workload||82|
|2L-768H-TH64 (big network with many parameters)|
|EdgeDRNN + Small memory workload||613|
|EdgeDRNN + Large memory workload||595|
The RNN inference time varies between 50 us to 0.5 ms across the different network sizes. During this inference time, the PS is free for other tasks (e.g. computing features) and only needs to check if the RNN update is finished when these tasks are completed.
Iv-F Power Measurement
|Part||Wall Power (mW)||Percentage|
Table V shows the power breakdown of the MiniZed system. The total power is measured by a USB power meter; the PS, PL and static power is estimated by the Xilinx Power Analyzer. The whole system burns at most 2.3 W but the EdgeDRNN only consumes 66 mW. It is interesting to note that the DRAM power is about 8X more than the RNN logic. This result clearly shows that the RNN computation is memory dominated.
V-a Comparison with FPGA RNN Accelerators
|Platform||This Work||BBS ||DeltaRNN ||ESE ||DeepRnn |
|FPGA||XC7Z007S||Arria 10 GX1150||XC7Z100||XCKU060||XC7Z045|
|Dev. Kit Cost||$89||$4,495||$2,295||$3,295||$2,495|
|Weight Storage||Off-chip||On-chip & off-chip||On-chip||Off-chip||On-chip & off-chip|
|INT 16/8/0||INT 16/16/4||INT 16/16/0||INT 16/12/4||INT 16/16/0|
|1 Effective Sparsity||90.0%||87.5%||88.2%||88.7%||-|
|Number of MACs (Batch-1)||8||4096||768||32||256|
|2 Peak Throughput (GOp/s)||2||1638.4||192||12.8||4.5|
|3 MAC Utilization||1010%||150%||630%||620%||15%|
|Wall Plug Power (W)||2.3||19.1||7.3||41.0+PC||-|
The effective sparsity of EdgeDRNN & DeltaRNN is calculated by Eq. 4.
Peak throughput is calculated by Eq. 6.
MAC utilization is the ratio between batch-1 throughput and the peak throughput of the accelerator.
Memory-bounded peak throughput is calculated by Eq. 8.
Normalized to the same frequency, DRAM interface bit width for weight fetch, number of MACs and activation & weight bit precision with EdgeDRNN. We assume the normalized numbers are obtained on the same MiniZed board and assume they have the same wall plug power consumption with EdgeDRNN. Detailed discussion is in Section V.A.
Table VI compares EdgeDRNN with other state-of-the-art FPGA RNN accelerators. Both BBS  and DeltaRNN were optimized for batch-1 inference by using all MACs for a single input sample. BBS can use DRAM to support large networks and has the highest batch-1 throughput among all accelerators; however the reported throughput number was obtained by buffering the whole network by using expensive on-chip memory. After compression, the network has around 0.8 MB parameters, which can be buffered on large FPGAs like the GX1150 used by BBS, but it is still too expensive for edge hardware platforms (e.g. MiniZed has only 0.2 MB on-chip memory). ESE  reuses weights fetched from off-chip memory to feed 1024 MACs for batch inference and achieved 2520 GOp/s total throughput; however only 32 out of 1024 MACs were used for each input sample limiting its batch-1 throughput. Except for EdgeDRNN and DeepRnn , other platforms are not designed for edge applications. BBS, DeltaRNN and ESE provide much higher throughput but their power consumption is around 3X-18X larger than EdgeDRNN and they require expensive FPGA development systems that are not very portable. By contrast, the small number of processing elements in EdgeDRNN is intentionally chosen to match the available memory bandwidth of the DRAM interface, since there is no point in having idle PEs.
To fairly compare architectures without the influence of different specifications of FPGA platforms, it makes sense to normalize the batch-1 throughput and other corresponding numbers of accelerators to the same number of PEs ()333Each PE has a single MAC unit., clock frequency ( MHz), DRAM interface bit width for weight fetch (64-bit) and bit precision of weights (INT8) & activations (INT16) as used by EdgeDRNN. We also assume that the normalized platforms are implemented on MiniZed having the same power consumption of EdgeDRNN. The normalized batch-1 throughput is defined below:
where is the memory-bounded peak throughput and is the bit width of the nonzero element index. To exploit weight sparsity by skipping zero elements in the weights, indices of nonzero weight elements have to be used and introduces off-chip memory overhead. Both BBS and ESE use for their tested networks. EdgeDRNN and DeltaRNN only need indices of valid columns corresponding to nonzero delta state vector elements, and they are calculated on-chip without introducing off-chip memory overhead; thus, for EdgeDRNN and DeltaRNN. In this normalization process, we assume the ideal case, in which normalized platforms reach the memory-bounded peak throughput and can fully utilize sparsity. Thus, Eq. 8 gives the upper bound throughput value of the normalized platform.
Table VI shows that EdgeDRNN achieves the highest normalized throughput, and an even higher normalized throughput than our previous BRAM-based DeltaRNN because of the improved pipeline and higher sparsity achieved. Compared with BBS, EdgeDRNN achieves only a small fraction of the total batch-1 throughput, but the normalization makes it clear that BBS achieves its high throughput by using on-chip BRAM, a huge number of MACs, and a higher clock frequency. Among all the accelerators, EdgeDRNN also shows the highest effective MAC utilization and the lowest wall plug power. Finally, the EdgeDRNN FPGA development kit is a factor of at least 25X cheaper than other FPGA RNNs, and the cost is comparable to the cheapest edge AI accelerators.
V-B Architectural Comparison
Fig. 12 compares the architecture and MxV flow of EdgeDRNN with BBS and ESE. We compare EdgeDRNN with ESE and BBS because they are also FPGA RNN accelerators using DRAM with high reported throughput. Both ESE and BBS exploit weight sparsity with load balancing techniques.
In ESE, interleaving rows of matrix elements are assigned to MAC units in the PE array and the MxV is computed column by column. To balance the workload and exploit weight sparsity better, the network weight matrix is pruned so that the number of nonzero elements assigned to each MAC unit is the same for the whole matrix. activation buffers (BUF) are required for MAC units, which immediately execute operations when nonzero activations and weights are available.
BBS balances the workload using structured pruning. Rows of a weight matrix are split into banks of equal length. Their pruning method forces the numbers of nonzero values to be the same across all banks. By assigning the same number of row banks to each MAC unit in the PE array, the workload is balanced. As shown on the right side of Fig. 12, each row of the matrix is equally divided into two banks respectively for MAC 0 and MAC 1 and the computation is done row by row. In this case, each MAC receives different activation elements and BUFs are required for MAC units. BBS also supports the buffering of a partial weight matrix on-chip to enhance throughput, which is useful for large FPGA platforms. The reported batch-1 throughput of BBS in Table VI is obtained with all network parameters on-chip, which is not practical on a small FPGA platform like MiniZed that has only 0.2 MB on-chip memory.
|Platform||This Work||NCS2 ||Jetson Nano ||Jetson TX2 ||GTX 1080 |
|Chip||XC7Z007S||Myriad X||Tegra X1||Tegra X2||GP104|
|Dev. Kit Cost||$89||$69||$99||$411||$500+PC|
|DRAM Type (Bus Width)||DDR3L (16-bit)||-||LPDDR4 (64-bit)||LPDDR4 (128-bit)||GDDR5X (256-bit)|
|DRAM Bandwidth (GB/s)||1.0||-||25.6||59.7||320|
|#Parameters||5.4 M||5.4 M||5.4 M|
|Bit Precision (A/W)||INT16/8||FP16||FP32||FP16||FP32||FP16||FP32||FP16|
|WER on TIDIGITS||1.1%||0.8%|
|1 Wall Plug Power (W)||2.3||1.7||7.2||7.1||8.2||8.1||96.6+PC||82.2+PC|
EdgeDRNN power was measured by a USB power meter. Power numbers of Jetson Nano and Jetson TX2 boards are measured by a Voltcraft 4500ADVANCED Energy Monitor. Power of GTX 1080 was measured by the nvidia-smi utility.
Unlike ESE and BBS, EdgeDRNN includes an extra unit to compute delta state vectors. Similar to ESE, EdgeDRNN also assigns interleaving rows to MAC units and computes MxV column by column; however, all MAC units share the same delta state vector elements; thus, only 1 BUF (D-FIFO) is required.
Both ESE and BBS require indices of nonzero weight elements to realize zero-skipping. The indices cause overhead on memory access, reducing effective memory bandwidth. EdgeDRNN skips whole columns of computation and indices of valid columns are calculated on-the-fly to avoid memory overhead.
Moreover, ESE and BBS require extra Element-wise (E-wise) multiplication units for the RNN activation generation after MxV. EdgeDRNN reuses multipliers in the PE array by time-division multiplexing to save DSP and LUT resources. Element-wise addition is done by reusing adders in the PE array and also using a single 16-bit adder per PE, as shown in Fig. 5.
Our previous work, DeltaRNN , achieved high batch-1 throughput and MAC utilization with temporal sparsity, but it stored all network parameters on chip, making it unscalable. Meanwhile, EdgeDRNN is designed to match the external memory bandwidth available on any FPGA platform with external DRAM. The small number of MAC units along tall concatenated weight matrix columns, as shown in Fig. 6, makes the burst length long enough to maintain high DRAM controller efficiency for large networks.
V-C Comparison with an SNN Processor
We compare the performance metrics of TrueNorth , an application-specific integrated circuit (ASIC) SNN processor, on the TIDIGITS dataset. The system is reported to dissipate 38.6 mW power by using a feature extraction method that can be implemented directly on TrueNorth . We cannot easily compare the power numbers of this ASIC processor with the power dissipated by an FPGA which is a more general-purpose platform. To run TrueNorth, an interfacing FPGA that burns several Watts is needed so the system power would much higher. The reported accuracy from their work is only 95% which is lower than the 99% accuracy achieved by the quantized delta network reported in our previous work .
V-D Comparison with Commercial Platforms
Table VII compares EdgeDRNN with popular commercial platforms, including their cost and memory system bandwidth. All platforms are benchmarked on the same spoken digit recognition task (first 10,000 timesteps of the TIDIGITS
test set) using networks of the same size, except that the Intel Compute Stick 2 (NCS2) does not support GRU and was benchmarked with an LSTM network with a similar parameter count and trained with the same hyperparameters. The latency requirement of the recognition task is 10 ms which is determined by the frame stride. To meet this requirement, frames cannot be concatenated into a single tensor. The computation of the RNN is executed when there is a new frame.
For benchmark of GPUs, we used GRUs because we found that latency numbers of both FP32 and FP16 cuDNN GRU implementations are 3X lower than that of running the DeltaGRU algorithm using the NVIDIA cuSPARSE library. In addition, we removed peripheral devices from the Jetson board with the exclusion of the needed Ethernet cable to the PC. Because GPUs also need time to boost their clock frequency and to allocate memory, the first 50 timesteps of the test sequence are excluded. The power efficiency results show that EdgeDRNN still achieves over 5X higher system power efficiency compared to commercial ASIC and GPU products.
GPUs are throughput-oriented architectures suitable for neural network training with large batch sizes; however, it is not optimal for edge inference where batch-1 throughput is critical for achieving low latency. The claimed peak FP32 throughput of Jetson Nano , Jetson TX2  and GTX 1080  are respectively 0.5 TOp/s, 0.8 TOp/s and 9 TOp/s while the measured batch-1 throughput are only 1.9 GOp/s, 3.5 GOp/s and 20.5 GOp/s. The low batch-1 throughput of GPUs is because weights fetched from off-chip DRAM cannot be reused to fully utilize GPU cores. Fig. 13A shows the throughput of GTX 1080 approaches the claimed peak throughput with large batch sizes due to more weight data reuse; however, increasing batch size also causes worse latency numbers as shown in Fig. 13B. FP16 outperforms FP32 because of the smaller memory bottleneck.
Fig. 14 compares latency per frame on a test set sample. EdgeDRNN latency is lower during the silent or quieter periods (e.g. between 60 s and 80 s) when the input is changing slowly. EdgeDRNN is as quick as the desktop 1080 GPU and 5X quicker than the other platforms, despite having a DRAM bandwidth that is orders of magnitude slower.
In , we reported that EdgeDRNN ran the RNN for robotic control about 51X faster than the embedded BeagleBone Black platform with a ARM Cortex-A8 CPU, while burning about the same total power of 2W. Moreover, to compare the performance of EdgeDRNN and the ARM Cortex-A9 CPU on the PS side of MiniZed, we took the same 2L-128H-DeltaGRU network used in our previous real-time control demonstration  and measured the latency per frame on 1 minute test data (sample rate = 200 Hz), which are 1000 frames of motor encoder readings. Fig. 15 shows the latency of the ARM CPU and EdgeDRNN. The mean latency of the ARM CPU is 1281 s without sparsity and 428 s with sparsity. The mean latency of EdgeDRNN with sparsity is 16 s, therefore EdgeDRNN is 27X faster than the ARM CPU which exploits temporal sparsity in the same network. In the case of the robotic task, EdgeDRNN runs the network 300X faster than the required maximum latency of 5ms.
The 2 W EdgeDRNN runs batch-1 RNNs as fast as a 200 W GPU+PC, and its power efficiency is at least a factor of 4X higher than any of the commercial edge AI platforms in the benchmark. We found that the batch-1 RNN throughput numbers of commercial GPUs are a factor of over 100X less than their claimed peak throughput. Using the delta network to exploit temporal sparsity allows a modest number of 8 PEs to achieve an effective 162 Op per clock cycle, equivalent to an MAC utilization efficiency of over 1000%. EdgeDRNN uses a standard AXI4 interface for weight fetches; thus it can be scaled up to larger FPGA platforms by simply increasing the number of PEs to match the available memory bandwidth provided by on-chip BRAM or off-chip DRAM. Thus using temporal sparsity in delta activation vectors allows the arithmetic units on this task to effectively compute 10X more operations with the same amount of memory access.
The delta threshold allows instantaneous trade-off of accuracy versus latency. Future work could exploit a dynamic trade-off of accuracy versus latency to quickly converge onto optimal values in a guided search.
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