Deterministic Computations on a PRAM with Static Processor and Memory Faults

12/31/2017
by   Bogdan S. Chlebus, et al.
0

We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. We develop a deterministic simulation of a fully operational PRAM on a similar faulty machine which has constant fractions of faults among processors and memory cells. The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and a constant fraction of m memory cells. The simulation is in two phases: it starts with preprocessing, which is followed by the simulation proper performed in a step-by-step fashion. Preprocessing is performed in time O((m/n+ n) n). The slowdown of a step-by-step part of the simulation is O( m).

READ FULL TEXT

page 1

page 2

page 3

page 4

research
06/24/2019

A formalisation of the SPARC TSO memory model for multi-core machine code

SPARC processors have many applications in mission-critical industries s...
research
06/23/2022

INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling

Modern and future processors need to remain functionally correct in the ...
research
01/16/2018

Trends in Processor Architecture

This paper presents an overview of the main trends in processor architec...
research
05/15/2018

The Parallel Persistent Memory Model

We consider a parallel computational model that consists of P processors...
research
08/07/2017

VART: A Tool for the Automatic Detection of Regression Faults

In this paper we present VART, a tool for automatically revealing regres...
research
01/04/2018

An Implementation of Back-Propagation Learning on GF11, a Large SIMD Parallel Computer

Current connectionist simulations require huge computational resources. ...
research
07/19/2017

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility

The memory model for RISC-V, a newly developed open source ISA, has not ...

Please sign up or login with your details

Forgot password? Click here to reset