There has been a rise in the popularity of hardware accelerators, especially in the mobile domain (SoCs). This includes designing domain-specific accelerators/implementations for machine learning, graph processing , DNA-Alignment algorithms , Neuromorphic algorithms  etc.
Memory design is a crucial component of hardware accelerators, where designers require stringent architectures for memory accesses to gain high-performance. A high-performance spatial accelerator (as shown in Fig 1) can efficiently exploit the parallelism of the data-flow graph, and execute multiple operations in parallel. Hence, multiport memories may be required to support single-cycle access in hardware.
However, there is currently no inherent EDA support for multiport memories beyond 2-ports, hence for utilizing more ports, a circuit-level implementation has to be done from scratch. Algorithmic Multiported Memory (AMM) allows us to utilize multiple ports starting from the same circuit-level 2-port configurations already provided by the memory compilers of chip-manufacturing vendors.
Further, it has been shown that Algorithmic multi-ported memories are more efficient, in terms of resource usage and performance, when compared with synthesizing the same multiport memory with registers and has similar performance compared with a Circuit-level implementation .
While, conventional approaches such as banking (which provides memory ports with conflicts), and mutli-pumping (which degrades the maximum external operating frequency), AMMs provide no-conflict based design that can operate at the maximum frequency.
These properties of AMM can be leveraged in rapidly understanding the design space available in accelerator with several optimizations possible for high performance or EDP maximization objectives.
Most of the previous works of AMMs have explored its use cases on FPGAs [6, 7], but the limited resource on FPGA constraints the full potential of their design space exploration. The limited number of BRAMs, F/F, slice LUTs are unable to explore important design factors of AMM such as the number of ports, memory depth and banking structures important in high-performance accelerators.
The contributions of our work are :
We extend the design space exploration for memories in Application-specific accelerators for high performance (in terms of execution time) by utilizing Algorithmic Multi-port Memories.
We synthesize scratchpad and cache-memory AMM designs in different memory cells, port configurations and memory depth to improve design space exploration in Pre-RTL Accelerators. Then we schedule the multi-port memory instructions in the Aladdin framework by extracting parallelism from the algorithm trace.
The efficient use of AMMs (as true multiport memories) compared to banking structures for high-performance design is dependent upon the spatial memory access-patterns of the application. We empirically depict this on the MachSuite benchmark and show that AMMs work well for high-performance design requirements, for applications with low spatial locality ( 0.3) in memory access patterns.
Ii Algorithmic Multi-port Memories
The two-prominent approaches in AMMs include Non-table-based and Table-based.
Ii-a Non-Table-Based Approaches
The Non-table XOR-based approach (NTX-Rd/ NTX-Wr) proposed in , store xor-ed parity data in multiple banks to support multiple reads and enable multiple writes. It was developed further in HB-NTX-RdWr which can scale the number of ports with a systematic flow.
H-NTX-Rd : H-NTX-Rd follows the encoding scheme as, Bank0 stores Data0 directly, Bank 1 stores Data1 and Reference Bank stores D0 D1. In case 2 Reads are directed to the same Bank, say Bank0, then the second read at offset i, can be retrieved as, Bank1[i] Ref[i].
B-NTX-Wr : B-NTX-Wr follows the encoding scheme as, Bank0 stores Data0 Ref, and Bank1 stores Data1 Ref. In the Non-Conflict case, say two writes W0[i] and W1[j], are in different Banks, then data is stored as D0[i] = W0[i] Ref[i] and D1[j] = W1[j] Ref[j]. In the Conflict-based requests, say both W0 and W1 at Bank 0, then data is stored as, D0[i] = W0[i] Ref[i], T = D1[j] Ref[j], Ref[j] = W1[j] D0[j] and D1[j] = Ref[j] T.
HB-NTX-RdWr : HB-NTX-RdWr (shown in Fig. 2) adds reads ports following the scheme of H-NTX-Rd and write ports following the B-NTX-Wr write approach. Say, for building a 2R2W memory, all the banks should be made 4R1W following the H-NTX-Rd and the converted to 2R2W following the B-NTX-Wr method (Total read ports reduce because each read will access all the Banks and Each write will access it’s own bank and the reference bank).
Ii-B Table-Based Approaches
Table-based approaches use multiple memory modules to support multiple accesses and use lookup tables to avoid module conflict and track the most up-to-date values.
The live value table (LVT) approach utilizes LUT to track the most updated location of the stored data. Read requests query the table to access data at the correct memory location. The multiple read requests are handled by replicating memory banks, and multiple write requests are supported by the LVT.
Usually, Non-table-based AMMs have shorter latencies when compared with table-based designs. Table-based AMMs pose smaller area and lower power consumption than non-table-based AMMs. Other approaches include Table-Based Remap Table(TBRemap), (TBLVT-HB-NTX-RdWr) and enhancing Table-Based techniques with Reduce Lookup Tables. [9, 10, 11, 12, 13, 8, 14]
Iii Experimental Setup
All the AMM designs discussed above (both Table and Non-table Based), were synthesized and the best performing configurations (of a given read-write port and port depth) were chosen to be incorporated in the power, area and latency models in the Aladdin Framework. The write-path and read-path logic (in Verilog HDL) was synthesized in Synopsys Design Compiler at UMC 45nm. CACTI is used to estimate the performance of different SRAM modules. By combining the synthesis results of read-path and write-path logic, and estimation from CACTI (SRAM) we can evaluate the overall performance and cost of an AMM design.
Iii-B Flow of Analyzing
In this section, we describe the flow of analysis in the Aladdin Framework  and the methodology used for incorporating multi-port memory access.
The Aladdin Framework transforms the source code for the accelerators to output configuration results including clock speed, the number of cycles, components in the synthesized design, power and area breakdown of each component and its total utilization. The code is compiled to the LLMV IR and a Data Dependency Graph (DDG) is extracted from it. Graph Transformations are applied according to the user-defined configurations, where multiple memory banks can be specified by array partitioning, multi-issue ALUs may be constructed by loop unrolling and flattening etc. Further, caches and their structure can be configured and registers and scratchpad memory can be utilized to club or unroll memory elements.
From these specifications, a cycle-accurate execution takes place, from the resources calculated earlier and power, area and execution time are determined.
For utilizing the multiport memories, we add our own power, area and latency results from the synthesis as described above.
Iii-C Scheduling for Multiport Memories
The cycle-accurate simulator schedules the data flow graph, which is represented as a DAG that extracts memory level parallelism of memory instructions and instruction-level parallelism of ALU operations.
The DAG allows multiple accesses and the scheduler then issues the number of accesses requested, accordingly from the read-write port configurations and port width defined by the user.
Iv-a Design Space Exploration of AMM
In the design space exploration of any accelerator design, different compositions are possible by loop-unrolling, array-partitioning, changing word-size and number of read and write ports. We use a sweep of such compositions, in the implemented Mem-Aladdin Framework.
We analyze using the MachSuite benchmark which includes both compute-intensive benchmarks such as, Stencil, where arithmetic and functional units often dominate execution time and power, and memory-bound workloads, e.g., Sort, to give modelling capabilities across multiple dimensions.
From the benchmarks suites, the four benchmarks for discussion (FFT-Strided, GEMM-NCUBED, KMP, MD-KNN) are chosen accordingly with varying spatial locality (discussed ahead) and the memory size requirements in execution.
In terms of the memory configurations, a wide range of designs are possible by partitioning large arrays into scratchpad memories allowing parallel access.
The arrays which have single-stride access can be partitioned cyclically. The parallel access with a number of ALU/FPU can allow faster execution but increase the power consumption and area of the design. However, for different strides, the accesses will be different. The array-partitioning based design based exploration is dependent on the spatial locality of the array in the algorithm. Multiport Memory designs provide non-conflict based access and independent of the stride access.
Figure 4 shows the design space exploration by varying these parameters for four different benchmarks, chosen to demonstrate and understand the benefits of algorithmic multiport memory. The designs utilizing multiport memory are marked in blue and with single port-memories are shown in red. The design space can be increased (shaded in blue) by using multiport memory creating high-performance accelerators that were not possible earlier.
Iv-B Spatial Locality
Both stride and length of the word are directly correlated with performance in array-partitioned based designs. Algorithms with high-stride will perform poorly in speed due to high bank-conflicts and having larger word-size of each element will increase the area and power consumption of the design. Comparing Array-partitioning based banking and algorithmic multiport memory is important to understand the need of using the later in chip designs.
Spatial locality measures where a program’s memory accesses occur in relation to each other. To summarize the spatial locality across MachSuite, we use a simple metric defined by Weinberg et al.  :
where stride is the difference between consecutive address elements referenced and length is the number of of elements with same stride in a load/store instruction.
The spatial locality on the MachSuite benchmark is shown in Fig 5. From equation 1, programs with stride-one code have high spatial locality. Stride-one code is available in byte-oriented programs like KMP and AES, where double-precision programs (e.g. FFT-Strided) have a minimum stride distance of 8 bytes.
From Fig 4, it is seen that the performance of algorithmic multi-port memory is similar to having a large number of small partitions of the array.
For most of the benchmarks, the Power Consumption vs Execution time trade-off for both AMM and banking-based designs is similar. It can be due to the fact banking-based design use multiple smaller memory sizes and are slower due to conflicts which can easily be offset by the using larger memory AMM design. For similar speed both the approaches take usually similar number of cycles.
Iv-C Qunatifying Correlation between AMM performance and Spatial Locality
The performance in AMM is correlated here to spatial locality of the benchmarks. Since KMP uses 1-bit word access with stride 1, it has very less number of bank conflicts in array-partitioning so a true-multiport design isn’t necessary. Hence, in the area required vs the number of cycles, the area required by AMM is higher in KMP (shaded green) whereas it is nearly equal in other cases. The design space using AMM uses more area, hence performs worse than array-partitioning design.
In Gemm-Ncubed design in Fig 4 (c), the AMM performs better with correct word size and read/write port configuration. The spatial locality of Gemm is low because of higher word-size since computation is done in floating-point numbers.
Since only the area required for particular execution time varies significantly in AMM based designs vs banking-based structures, we compare for area-requirements only. This comparison can be represented as a single metric over the entire design space, by taking the geometric mean over the observed points. More Specifically,
Performance Ratio = , where is the area-point of banking-structure, is the area-point of AMM at similar execution times.
Further, this analysis can only be done for benchmarks with high number of memory accesses compared to computation operations. Hence, Pre-RTL design of only a few benchmarks can be chosen to demonstrate this behaviour.
The correlation of performance of AMM-based design (taking banking-structures as baseline) with Spatial Locality is also shown in Fig 5.
Hence, AMMs can be effectively utilized to provide non-conflict multi-port memory access for designing high-performance accelerators of applications with low spatial locality ( 0.3) in memory access patterns.
In this work, we present a method to incorporate AMM based scratchpad and cache-memory multi-port configuration to improve design space exploration in Pre-RTL Accelerators. We describe a method which schedules multi-port memory instructions in the Aladdin framework by extracting parallelism from the algorithm trace. We synthesize different AMM designs, memory depth, port configurations, banking structures, building memory cells. From our analysis on applications from the MachSuite (accelerator benchmark suite), we gain insight into the use of AMMs (as true multiport memories) for high performance in applications with low spatial locality in memory access patterns which is quantified by empirical observations.
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